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研究生:許家豪
研究生(外文):Chia-Hao Hsu
論文名稱:具有高速及低功率消耗之10-T全加法器的設計及分析
論文名稱(外文):Design and analysis of 10-T full adders with high speed and low power characteristic
指導教授:李博明
指導教授(外文):Po-Ming Lee
學位類別:碩士
校院名稱:南台科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:57
中文關鍵詞:10-T全加法器
外文關鍵詞:10-Tfull adder
相關次數:
  • 被引用被引用:0
  • 點閱點閱:203
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  • 下載下載:30
  • 收藏至我的研究室書目清單書目收藏:0
VLSI設計已正式邁入SOC(system on chip)時代,許多各種不同功能的電路都被集中在同一顆IC上面,在一個數位系統中,全加法器是一個經常被使用到的算術單元,如CPU裡面的算術邏輯單元(Arithmetic Logic Unit, ALU),或是各種特殊應用積體電路(Application Specific Integrated Circuit, ASIC),以及各式密碼系統的應用。若是我們能夠將全加法器的延遲時間及功率消耗改善,勢必會對電路整體的效能有所幫助,所以許多不同架構的全加法器就此孕育而生,截至目前為止,以十顆電晶體(10-T)所構成的全加法器為最精簡的,而許多國內外之全加法器文獻亦以10-T的架構為發展目標,因此我們的主要目標在於設計出可實現之具有高速及低功率消耗特性的10-T全加法器。
本文提出六個新的10-T全加法器架構,對照現有文獻中的10-T全加法器架構,我們所提出的某些架構在不論是在功率消耗或是延遲時間上均擁有較佳的表現,因此若將我們所設計的應用在需要高速與低耗電的數位電路設計裡,將會擁有較佳的效能。
The design of VLSI has into SOC(system-on-chip)era, many different functions are integrated into a single chip. Full adders is usually adopted in the arithmetic logic unit of a digital system, e.g. ALU inside a CPU, many kinds of ASIC(Application Specific Integrated Circuit)chips, and various of cryptographic systems. If we can refine the architecture of a full adder, the performance of a chip using the refined full adder will be increased. Many different architectures of a full adder were proposed, the structure of 10-T(10 transistors)full adder was a balanced design regarding transistor counts and performance. Thus, we try to design 10-T full adder in this thesis.
Six novel 10-T full adder structures are proposed in this thesis, The comparison between the proposed adders and the prior works was also performed. The proposed designs possess the advantages of better performance of power consumption and time delay. If will be a better alternative to use the proposed full adder architecture in a high speed as well as low power digital circuit.
摘要 iv
英文摘要 v
誌謝 vi
目次 vii
表目錄 ix
圖目錄 x
第一章 緒論 1
1.1 研究背景與動機 1
1.2 研究目的 3
1.3 章節結構 4
第二章 文獻探討 5
2.1 功率消耗 5
2.2 10-T全加法器文獻回顧 8
2.2.1 SERF ADDER 8
2.2.2 YUKE ADDER 9
2.2.3 Junming ADDER 13
2.2.4 N10-T與P-10 ADDER 14
第三章 研究方法 16
3.1 位元加法器,(m, k)-counters 16
3.1.1 半加法器 17
3.1.2 全加法器 18
3.1.3 (m, k)-counters 21
3.2 以GDI架構實現之10-T全加法器 22
3.2.1 GDI簡介 22
3.2.2 GDI 10-T全加法器 27
3.3 以XOR-XNOR產生器所構成之10-T全加法器 33
第四章 模擬及實作 37
4.1 模擬環境 37
4.2 模擬結果 38
4.3 實作結果 46
4.3.1 以TSMC 0.35um製程的實作結果 47
4.3.2 以TSMC 0.18um製程的實作結果 51
4.4 實作心得 54
第五章 結論及未來研究方向 55

參考文獻 56
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10.Lu Junming, Shu Yan, Lin Zhenghui and Wang Ling, “A novel 10-transistor low-power high-speed full adder cell”, 6th International Conference on Solid-State and Integrated-Circuit Technology, 2001. Proceedings., pp. 155 - 1158 vol.2, 22-25 Oct. 2001.
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