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研究生:曾建平
研究生(外文):Jian-Ping Zeng
論文名稱:H.264/AVC去區塊效應濾波器之VLSI架構設計
論文名稱(外文):VLSI Architecture for Deblocking Filter in H.264/AVC
指導教授:余兆棠余兆棠引用關係
指導教授(外文):Chao-Tang Yu
學位類別:碩士
校院名稱:南台科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:53
中文關鍵詞:去區塊效應濾波器
外文關鍵詞:Deblocking Filter
相關次數:
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MPEG-4 Part 10 Advanced Video Coding(AVC)與ITU-T制定之H.264是最新的視訊國際壓縮標準,H.264/AVC採用最新的革命性視訊壓縮技術,可達到利用最少之壓縮視訊資料但能提供絕佳視訊品質之目的,因此採用此技術之視訊編解碼器比前一代H.263技術的編解碼器更節省傳輸頻寬與資料儲存成本。H.264/AVC技術之系統只要H.263技術之系統一半的資料傳輸率即可提供與採用MPEG-2壓縮技術一樣的畫質。本論文研究H.264/AVC標準之解碼器,根據H.264/AVC解碼器的複雜度模擬中,模擬結果顯示去區塊效應濾波器(deblocking filter)是解碼器內最複雜的部分,佔了大約36%的運算資料與時間,其次依序是內插(interpolation)電路、熵編碼(entropy coding)電路以及資料重建電路分別佔了大約22%、13%與13%的運算資料與時間。顯然要改進H.264/AVC視訊解碼器之設計,由去區塊效應濾波器著手,其收效最為顯著,因此本論文主要研究去區塊效應濾波器之VLSI架構。以減少記憶體存取次數為設計考量,提出一個PBSR (Pipeline Buffer Shift Registers)架構之濾波器使其可以同時處理水平邊界與垂直邊界的去區塊效應,奠基於此架構,進一步使用Window-based架構設計一適合處理高畫質電視(high-definition television, HDTV)的去區塊效應濾波器,以Verilog HDL實現所提出之PBSR架構與Window-based架構之去區塊效應濾波器,再利用模擬軟體(ModelSim)分別驗證其功能,完成之去區塊效應濾波器經模擬結果顯示所提出的架構處理速度比先前已提出的去區塊效應濾波器架構快,且記憶體存取次數比標準架構和先前已提出的架構相較減少78.75%和52.5%。
The new video coding standard recommendation H.264 of ITU-T, also known as International Standard 14496-10 or MPEG-4 Part 10 Advanced Video Coding (AVC) of ISO/IEC, has been developed. It significantly outperforms the previous ones (H.261, MPEG-1 Video, MPEG-2 Video, H.263, and MPEG-4 Visual or part 2) in the aspect of bit-rate reduction. At the same time, preliminary studies using software based on this new standard, suggest that H.264 offers up to 50% better compression than MPEG-2 and up to 30% better than H.263+ and MPEG-4 advanced simple profile. In the complexity simulation of H.264/AVC decoder/encoder, the deblocking filter is the most complexity part. Obviously to improve decoder/encoder performance, the deblocking filter will be considered first to be improved. In this thesis, we study and analyze deblocking filter in H.264/AVC. In order to reduce the number of memory references and thus improve overall system performance, we propose an advanced filtering process order with an efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. The processing capability of the proposed architecture is very appropriate for real-time deblocking of high-definition television (HDTV, 1920x1080 pixels/frame, 60 frames/video signals) video operation at 60 MHz. The proposed PBSR(Pipeline Buffer Shift Registers) and Window-based architecture deblocking filters are implemented by using Verilog HDL. The function of the implemented deblocking filters is also verified by ModelSim. It can be shown that the number of the total memory references is reduced by 78.75% and 52.5% respectively compared to the basic and advanced architectures of the previous works. As a result, the performance of our configurable window-based architecture with parallel engine significantly outperforms the previous designs in terms of memory references and processing cycles.
摘 要 i
Abstract ii
致 謝 iii
目 次 iv
圖目錄 vi
表目錄 viii
表目錄 viii
第一章 緒論 1
1.1 研究動機與目的 1
1.2 論文架構 4
第二章 H.264/AVC 5
2.1 H.264/AVC視訊壓縮標準 5
2.2 H.264/AVC標準之編解碼 6
2.2.1 轉換與量化 9
2.2.2 熵編碼 11
2.2.3 圖間預測 12
2.2.4 圖內預測 14
2.2.5 去區塊效應濾波器 15
2.3 去區塊效應濾波器 17
2.3.1 處理順序 17
2.3.2 邊界強度 21
2.3.3 濾波 23
第三章 去區塊效應濾波器VLSI架構之設計 26
3.1 濾波單元(EFU) 27
3.2 PBSR架構 29
3.3 Window-based架構 34
第四章 去區塊效應濾波器之實現與效能分析 40
4.1 去區塊效應濾波器功能驗證 41
4.2 去區塊效應濾波器效能分析與比較 47
4.2.1 記憶體存取次數 47
4.2.2 整體系統效能 48
4.2.3 硬體實現與分析 49
第五章 結論 51
[1]“Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec. H.264/ISO/IEC 14 496-10 AVC,” in Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVTG050, 2003.
[2]“Special Issue on the H.264/AVC Video Coding Standard,” IEEE Trans. Circuits Syst. Video Tech., Vol. 13, July 2003.
[3]ITU-T Recommendation H.264, “Advanced video coding for generic audiovisual services,” March 2003.
[4]ITU-T Recommendation H.261, “Video codec for audiovisual services at p X 64 kbits/s,” March 1993.
[5]ITU-T Recommend H.263, “Video coding for low bit rate communication,” 1998.
[6]C.-M. Chen, C.-H. Chen, J.-P. Zeng and C.-T. Yu, “Windows Processing for Deblocking Filter in H.264/AVC,” in the proceeding of the 32nd Annual Conference of the IEEE Industrial Electronics, November 7-10, 2006.
[7]Iain E. G. Richardson, “H.264 and MPEG-4 Video Compression, Video Coding for Next-generation Multimedia,” John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England, 2003.
[8]C.-M. Chen, J.-P. Zeng, C.-H. Chen, C.-T. Yu and Y.-P. Chang, “Window Architecture for Deblocking Filter in H.264/AVC,” The 6th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT 2006), August 2006.
[9]Join Ostermann, Jan Bormans, Peter List, Detlev Marpe, Matthias Narroschke, Fernando Pereira, Thomas Stockhammer and Thomas Wedi, “Video Coding with H.264/AVC: Tools, Performance, and Complexity,” IEEE Circuit and Systems Magazine, pp. 7-28, 2004.
[10]C.-M. CHEN and C.-H. CHEN, “An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC,” IEICE TRANS. INF. & SYST., VOL.E90–D, NO.1 JANUARY 2007
[11]ITU-T Recommendation H.264, “Advanced video coding for generic audiovisual services,” 2003.
[12]Yu-Wen Huang, To-Wei Chen, Bing-Yu Hsieh, Tu-Chih Wang, Te-Hao Chang and Liang-Gee Chen, “Architecture Design for De-blocking Filter in H.264/JVT/AVC,” Proc. IEEE Conf. on Multimedia and Expo, pp. 693-696, 2003.
[13]Lingfeng Li, Satoshi Goto and Takeshi Ikenaga, “A Highly Parallel Architecture for Deblocking Filter in H.264/AVC,” IEICE Transactions on Information and Systems, pp. 1623-1629, Vol. E88-D, No.7, July 2005.
[14]Bin Sheng, Wen Gao and Di Wu, “An Implemented Architecture of Deblocking Filter for H.264/AVC,” IEEE International Conference on Image Processing (ICIP’04), pp. 665-668, Vol.1, Oct. 2004.
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