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研究生:洪萬得
研究生(外文):Wan-Te Hung
論文名稱:非對稱型雙閘極金氧半場效電晶體之次臨界行為研究
論文名稱(外文):The Investigation on Subthreshold Behavior Model for Asymmetrical Double-gate MOSFETs
指導教授:江德光
指導教授(外文):Te-Kuang Chiang
學位類別:碩士
校院名稱:南台科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:63
中文關鍵詞:非對稱次臨界雙閘極
外文關鍵詞:AsymmetricalDouble-GateSubthreshold
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近年來金氧半場效電晶體具雙閘極結構已被廣泛的研究並且計劃取代傳統的電晶體和SOI技術,和傳統CMOS相較之下,雙閘極式金氧半場效電晶體在尺度的微縮上具有較大的空間與優勢,又在元件設計快速之循環週期上,促使以上之新型元件結構有其必要性,並且亦提供於電路設計上有更好的選擇。
基於摻雜雙閘極結構之矽基體和閘極絕緣層的帕森方程式之完全封閉型解,於本研究中吾人根據分離變數之疊加法與簡化二維邊界條件推導出此分析模型,此模型顯示出電位分佈、短通道臨界電壓縮減、尺度微縮空間、次臨界電流、次臨界斜率、汲極偏壓引致通道位能障降低效應,此模型之演算結果與模擬數據相當接近,並發現在摻雜非對稱型雙閘極電晶體能夠有效的減少次臨界區漏電流。
In recent years, studies about Double-Gate (DG) transistor have successively been proposed, and have attracted a lot of attention. As CMOS is scaled to the limit, dou-ble-gate (DG) MOSFET becomes increasingly important. A number of authors have ap-plied various simplifying assumptions to model the SCE of DG fully-depleted MOS-FETs analytically. Some of them make use of a parabolic potential approximation ap-proach for the device in the direction perpendicular to the surface. This results in a scale length proportional to the oxide and the silicon thickness. Large errors occur when one of thickness is much less than the other. Other approaches apply the superposition method to solve the 2-D boundary-value problem for the bulk MOSFETs. Most of them only put focus on device scaling scheme, threshold degradation by ignoring the 2-D ef-fects in the gate oxide. In order to give insight into the device physics, we need to de-velop a consolidated threshold voltage model for the DG transistor with fully 2-D ef-fects included in both silicon and gate oxide regions.
In this thesis, we successfully develop a physical and analytical threshold voltage model for fully depleted Asymmetric DG MOSFETs by use of the 2-D analytical solu-tion in the entire region of the device based on fully closed-form solutions of Poisson’s equation in both regions of Si body and gate insulator. Without any fitting parameters, these analytical results are useful in predictive compact modeling of Asymmetric DG MOSFETs. The model shows the distribution of electric potential, short channel thresh-old voltage roll-off (ΔVTH), subthreshold current, subthreshold slope (Swing) and drain-induced barrier lowering (DIBL) effects. The new model is verified by published numerical simulations with close agreement. Due to its computational efficiency, this model can be applied for SPICE simulation.
摘要 i
Abstract ii
Acknowledgements iii
Contents iv
List of Figures vi
Chapter 1 Introduction 1
1.1 VLSI Overview 1
1.2 Asymmetric Double-Gate MOSFETs Survey 4
1.3 Motive of the Thesis 6
Chapter 2 Two Dimensional Model for Doped Asymmetrical Double-Gate
MOSFETs 7
2.1 Motive 7
2.2 Model Derivation 8
2.3 2D Boundary Conditions Value Problem 11
2.4 Scaling Length 14
2.5 Coefficients Solution 18
2.6 2D Generalized Potential Model 23
2.7 Minimum Channel Potential 25
2.8 Physical Threshold Voltage Roll-off Model 27
2.9 Results and Discussion 31
Chapter 3 2D Subthreshold Current Model for Doped Asymmetric Double
Gate MOSFETs 34
3.1 Motive 34
3.2 Subthreshold Slope Model 36
3.3 Analytic Subthreshold Current Model 39
3.4 Results and Discussion 43
Chapter 4 Subthreshold Model for Asymmetric Double-Gate MOSFETs
with High-k Gate Dielectrics 47
4.1 Motive 47
4.2 Scaling Length with High-K Gate Dielectrics 49
4.3 Asymmetric Double-Gate Model With High-k Gate Dielectric 51
4.4 Results and Discussion 56
Chapter 5 Conclusions and Future Works 57
5.1 Conclusions 57
5.2 Future Works 57
Publications List 58
References 59
Introduction of the Author 63
1.R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. Leblanc, “Design of ion-implanted MOSFET’s with very small physical dimen-sions,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 256-268, May 1974.
2.R. R. Troutman, “VLSI limitation from drain-induced barrier lowering,” IEEE Trans. Electron Devices, vol. ED-26, pp. 461-469, April 1979.
3.H. C. Poon, L. D. Yau, R. L. Johnston, and D. Beecham, ”DC model for short-channel IGFET’s” in IEDM Tech. Dig., 1974, pp. 156-159.
4.K. K. Young, “Short-channel effect in fully-depleted SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 36, pp. 399-402, Feb. 1989.
5.S. Veeraraghavan and J. G. Fossum, “A physical short-channel model for the thin-film SO1 MOSFET applicable to device and circuit CAD,” IEEE Trans. Elec-tron Devices, vol. 35, pp. 1866-1874, 1988.
6.A.Vandooren, S. Cristoloveanu, and J. P. Colinge, “The Dynamic Conductance and Transconductance in Double-Gate (Gate- All- Around) SOI Devices,” SOI Conf. Proc., pp. 116-117, 2000.
7.J.-P. Colinge, “Thin-film SO1 technology: The solution to many submicron CMOS problems,”lEEE IEDM Tech. Dig., pp. 817-820, 1989.
8.P. C. Yeh and J. Fossum, “Physical subthreshold MOSFET modeling applied to vi-able design of deep-submicrometer fully-depleted SOI lowvoltage CMOS technol-ogy,” IEEE Trans. Electron Devices, vol. 42, pp. 1605–1613, Sept. 1995.
9.S. Thompson et al., IEDM Tech. Dig, 2002.
10.C.Diaz et al., IEDM Tech. Dig 2003.
11.D.V. Singh et al., IEEE Int. SOI conf., 2005.
12.C. Gallon et al., Jap. Joum. App. Phys., 2006.
13.J. B. Kuo and S. C. Lin, “Low-Voltage SOI CMOS VLSI Devices and Circuits.” New York: Wiley, 2001.
14.D. Hisamoto, "FD/DG-SOI MOSFET-A Variable Approach to Overcoming the De-vice Scaling Limit," IEDM Dig., 2001.
15.D. Frank, S. Laux, and M. Fischetti, “Monte Carlo simulation of a 30-nm dual-gate MOSFET:Howfar can silicon go?,” in IEDM Tech. Dig., 1992, p. 553.
16.H.-S. P. Wong, D. J. Frank, and P. M. Solomon, “Device design considerations for double-gate, ground-plain, and single-gated ultrathin SOI MOSFETs at the 25 nm channel length generation,” in IEDM Tech. Dig., 1998, p. 407.
17.H.-S. P.Wong, D. J. Frank, Y. Taur, and J. M. C. Stork, “Design and performance considerations for sub-0.1 _m double-gate SOI MOSFETs,” in IEDM Tech. Dig., 1994, p. 747.
18.D. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, “Device scaling limits of Si MOSFETs and their application dependence,” Proc. IEEE, vol. 89, pp. 259–288, Mar. 2001.
19.F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance,” IEEE Electron Device Lett., vol. EDL-8, p. 410, 1987.
20.K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling theory for double-gate SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 40, pp. 2326–2329, Dec. 1993.
21.D. J. Frank, Y. Taur, and H.-S. P. Wong, “Generalized scale length for two-dimensional effects in MOSFETs,” IEEE Electron Device Lett., vol. 19, pp. 385–387, Oct. 1998.
22.D. J. Frank, S. E. Laux, and M. V. Fischetti, “Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?,” in IEDM Tech. Dig., 1992, pp. 553–556.
23.H.-S. P. Wong, D. J. Frank, and P. M. Solomon, “Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation,” in IEDM Tech. Dig., 1998, pp. 407–410.
24.Z. Ren, R. Venugopal, S. Datta, M. Lundstrom, D. Jovanovic, and J. Fossum, “The ballistic nanotransistor: A simulation study,” in IEDM Tech. Dig., 2000, pp. 715–718.
25.J. G. Fossum, “Physical insights on double-gate MOSFETs,” in Proc. Dig. Gov-ernment Microcircuit Appl. Conf., Mar. 2001, pp. 322–325.
26.X. Liang, Y. Taur, “A 2-D Analytical Solution for SCEs in DG MOSFETs”, IEEE Transactions Electron Devices, vol.51, Issue 9, pp.385-1391, 2004.
27.K. Suzuki, Y. Tosaka, and T. Sugii, “Analytical threshold voltage model for short channel n+-p+ double-gate SOI MOSFETs,” IEEE Trans. Electron Devices, vol.43, pp.732-738, 1996.
28.G. Pei, V. Narayanan, Z. Liu, and E. C. Kan, “3D analytical subthreshold and quantum mechanical analyses of double-gate MOSFET,” in IEDM Tech. Dig., pp.531-534, 2001.
29.T. N. Nguyen, “Small-Geometry MOS transistors: Physics and modeling of sur-face- and buried-channel MOSFETs,” Ph.D. dissertation, Stanford Univ., Stanford, 1984.
30.S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.
31.Q. Chen, B. Agrawal, and J. D. Meindl, “A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs,” IEEE Trans. Electron Devices, vol.49, pp.1086-1090, 2002.
32.Y. Taur, L. H. Wann, and D. J. Frank, “25 nm CMOS design considerations”, in IEDM Tech. Dig., pp.789-792, 1998.
33.Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S. H. Lo, G. A. Sai-Halasz, R.G. Viswanathan, H. J. C. Wann, S. J. Wind, and H. S. P. Wong, “CMOS scaling into the nanometer regime”, Proc. IEEE, vol.85, no.4, pp. 486-504, 1997.
34.D. J. Frank, R. H. Dennard, and E. Nowak, “Device scaling limits of Si MOSFETs and their application dependences”, Proc. IEEE, vol.89, no.3, pp.259-288, 2001.
35.Y. Taur, “CMOS scaling beyond 0.1 um:how short can Si go”, in Proc.Symp. VLSI Technology, pp.6-9, 1999.
36.D. J. Wouters, J. P. Colinge, H. E. Maes, Subthreshold slope in thin-film SOI MOS-FETs, IEEE Transactions Electron Devices, vol.37, Issue 9, pp.2022–2033, 1990.
37.MEDICI Manual, Technology Modeling Associates, Inc., Palo Alto, CA, USA, 1996.
38.D. Jimenez, B. Iniguez, J. Sune, L.F. Marsal, J. Pallares, J. Roig, and D. Flores,” Continuous Analytic I-V Model for surrounding-gate MOSFETs,” IEEE Electron Device Letters, vol.25, no.8, pp.571-573, 2004.
39.J. S. Yuan and J. J. Liou, “Semiconductor Device Physics and Simulation,” Plenum Publishing Corporation, pp.67-68, 1998.
40.J. J. Liou, A. Ortiz-Conde, and F. Garcia-Sanchez, “Analysis and Design of MOS-FETs Modeling, Simulation, and Parameter Extraction”, Kluwer Academic Pub-lishers, pp.34-35, 2000.
41.S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOS-FET’s,” IEEE Electron Device Lett., vol.18, pp.206, 1997.
42.H. S. Momose, M. Ono, T. Yoshtomi, T. Ohguro, S. I. Nakamura, M. Saito, and H. Iwai, “1.5nm direct-tunneling gate oxide Si MOSFETs,” IEEE Trans. Electron De-vice, vol. 43, pp.1233, 1996.
43.C. Chaneliere, S. Four, J. L. Autran, R. A. B. Devine, and N. P. Sandler, “Properties of amorphous and crystalline Ta2O5 thin films deposited on Si from a Ta(OC2H5)5 precursor,” J. Appl. Phys., vol,83, no.9 ,pp.48-23, 1998.
44.Y. Ta u r, D.A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S.-H. Lo, G. A. Sai-Halasz, R. G. Viswanathan, H.-J. C. Wann, S. J. Wind, and H.-S. Wo n g , P roc. IEEE 85, 486 (1997).
45.Y. C. Yeo, T. J. King and Chenming Hu : Trans. Electron Devices 50 p.1027, 2003.
46.Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge Uni-versity Press, New York, 1998.
47.G. C. F. Yeap, S. Krishnan, and M. R. Lin, “Fringing-induced barrier lowering (FIBL) in sub-100-nm MOSFETs with high gate dielectrics,” Electron. Lett., vol.34, no.11, pp.1150-1152, 1998.
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