本論文主要依據非對稱多處理器設計概念實現需要複雜訊號處理與決策流程的語者辨識系統。並提出針對語者辨識問題改良的類神經演算法，使用競爭式學習法，並在類神經的訓練過程中的後期，強調了小範圍內的總體特徵。訓練後的模型可成為小範圍內的群體聚集中心，目的是為了使競爭式學習法的類神經網路可以和使用統計模型計算參數通過機率，且又保持類神經網路擁有很高分類正確率的優點。系統實現部分包括：可程式系統晶片設計(SOPC)、平行計算機架構(Parallel Computer Architecture)、系統軟硬體共同設計(Hardware Software Co-design)、作業系統的驅動方法與資源管理機制等，系統中包含ARM處理器與可被FPGA合成的NIOS II處理器，借助兩顆處理器不同的優勢互補，達成系統效能的提升。
依實驗結果針對語者辨識問題改良的類神經演算法，可承襲了向量量化低運算量的優點，更提高了訓練模型的辨別率，特別適合應用於運算處理能力與記憶體資源有限的嵌入式系統中。在經過雙處理器系統最佳化的系統分割後，系統可達成即時訊號處理的效能表現，並以語音辨識協同語者辨識達成雙重身份驗證機制，且有能力負擔複雜圖形使用者圖形介面。

The main contribution of this thesis is to develop an embedded speaker recognition system with Asymmetric Multiprocessing architecture, and propose an improved ANN algorithm for speaker identification applications. Artificial Neural Network process emphasizes overall features with small area vocal signal characteristics. Improved ANN model can be used for estimated probabilities and provide a high speaker identification rate based on Learning Vector Quantization (LVQ) trained codebooks. System implementation tasks can be divided into to System on Programmable Chip design (SOPC), Parallel Computer Architecture and Hardware Software Co-design. The proposed system is implemented on ARM-based and NIOS II-based embedded platforms to perform the speaker recognition function. The strengths of different processors are implemented in order to improve the overall system performance.
The experimental results show that the proposed improved ANN model gives a higher speaker identification and verification rate than the LVQ and GMM trained codebooks. The improved ANN model utilizes the low computational complexity of LVQ. This is important when the speaker identification is implemented on a computation limited embedded system. The system can reach the real time signal processing capability, while provide the capabilities of complicated GUI.

中文摘要 i
英文摘要 ii
目錄 ii
表目錄 iv
圖目錄 v
第一章 緒論 1
1.1 研究動機 1
1.2 文獻回顧 2
1.3 論文架構 5
第二章 相關知識 6
2.1 語音辨識概論 6
2.1.1 語音訊號前處理 6
2.1.2 擷取特徵參數 8
2.1.3 語者辨識方法 10
2.1.4 語音辨識方法 12
2.2 嵌入式系統實現方法 16
2.2.1 系統晶片設計 17
2.2.2 作業系統 19
2.2.3 軟硬體共同設計 20
第 三 章 改進語音辨識核心 23
3.1 學習向量量化 23
3.2 徑向基底函數類神經網路 27
3.3 神經網路結合統計與量化模型 28
第 四 章 系統架構 34
4.1 系統模型 34
4.2 軟硬體分割與系統最佳化 36
4.2.1 硬體設計 37
4.2.2 軟體設計 39
4.3 系統實現 41
4.3.1 主系統 41
4.3.2 協同處理系統 46
4.4 系統整合 52
4.4.1 介面硬體架構 53
4.4.2 介面軟體架構 57
第五章 實驗結果 62
5.1 實驗環境設定 62
5.2 語者分類引擎評估 63
5.2.1 辨識效果 64
5.2.2 執行效率 66
5.3 系統效能 68
5.3.1 主系統效能 68
5.3.2 協處理系統效能 69
5.4 系統測試 70
第六章 結論與未來展望 72
6.1 結論 72
6.2 未來展望 72
參考文獻 74

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