臺灣博碩士論文加值系統

隨著製程科技的日新月異，製程元件的微小化賦予超大型積體電路製造極大的整合力，原先許多電子產品需靠繁雜電子電路與元件組成的，現今在奈米製程上都可很輕易的將整個系統整合在一顆晶片上。然而奈米製程卻深受電路效能與良率不佳的窘境，深究其因乃製程上的一些缺失諸如光學微影、新製程物質缺陷所致，因此可製造性設計的議題對於積體電路設計者與電子設計自動化為必須考量的關鍵因素。目前針對實體設計上考量可製造性設計的文獻已於近來急速增加，然對於時脈繞線上仍未有著墨，而已提出的繞線方法也難以整合於時脈繞線上。為此，本文提出金屬線段層次安排的方法，藉由衝突圖形的建立與尋求每一層金屬線段的最大獨立解，於X時脈繞線後改善光學鄰近上線段過近及減少穿孔點數量來提升良率與可靠度。實驗數據顯示此法可有效解決線段重疊與線段過近的問題並減少79.12%的穿孔點數量，除此之外，本文亦針對此法產生的副作用提出因應之法並對於可製造性設計提出一套整合之架構。

As the advanced process and shrinking feature size integrate more and more functions on one chip, accompaniments are the problems of lithography and material defects affecting the yield and quality of the chip beyond nanometer process. Via defects and congested wires are not beneficial for manufacturing in clock network and they should be avoided in the design. In this thesis, we refine these defects by layer assignment and formulate this assigning problem as conflict graph. The conflict graph is solved by maximum independent sets in each layer recursively and experimental results show almost 79.12% reduction rate of vias and 100% avoidance of all wires suffered in serious optical proximity effect in X architecture clock tree. In addition, we also evaluate the side effects and propose some strategies for the integration of design for manufacturability.

中 文 摘 要...............................................i
ABSTRACT................................................iii
誌 謝.....................................................v
Contents................................................vii
List of Tables...........................................xi
List of Figures........................................xiii
Chapter 1 INTRODUCTION....................................1
1.1 Motivation............................................2
1.2 Thesis Goals..........................................3
1.3 Thesis Organization...................................3
Chapter 2 BACKGROUND......................................5
2.1 Clock Networks........................................5
2.1.1 Delay Model.........................................7
2.1.2 Clock Tree Construction.............................8
2.1.3 Manhattan and Non-Manhattan Architecture...........13
2.1.4 Power Estimation...................................14
2.2 Lithography and Resolution Enhancement Techniques(RET)....................................................15
2.2.1 Phase-Shifting Mask (PSM)..........................17
2.2.2 Optical Proximity Correction (OPC).................18
2.3 New Materials and Manufacture Defects................20
2.3.1 Antenna Effect.....................................20
2.3.2 Interconnect Via...................................23
2.3.3 Chemical Mechanical Polishing (CMP)................26
Chapter 3 PROBLEM DEFINITIONS AND PROPOSED METHODS.......29
3.1 Problem Definitions..................................30
3.1.1 Excessive Vias.....................................31
3.1.2 Error Wires and OPE Wires..........................32
3.1.3 Input and Output...................................34
3.2 Proposed Methods.....................................35
3.2.1 Clock Tree Construction............................36
3.2.1.1 Sequenced Geometry Matching Algorithm (SGMA).....37
3.2.1.2 Locating Tapping Points (LTP)....................39
3.2.1.3 Algorithm........................................43
3.2.2 Via Minimization in Layer Assignment...............45
3.2.2.1 Construction of Conflict Graph...................45
3.2.2.2 Maximum Independent Sets.........................48
3.2.2.3 Discussion for Error Assignment..................52
3.2.2.4 Partition Long Wires to Use Layers Efficiently...54
3.2.3 Consideration for Optical Proximity Correction.....55
3.2.4 Redundant Via Insertion (RVI)......................57
3.2.5 Wire Sizing for Zero Skew..........................59
3.3 Side Effects and Strategies..........................64
3.3.1 Crises of Antenna Effect...........................64
3.3.2 Optical Proximity Correction Consideration.........67
3.3.3 Phase Conflict in Phase-Shifting Mask..............68
3.3.4 Irregularity of Chemical Mechanical Polishing......69
Chapter 4 EXPERIMENTAL RESULTS...........................71
4.1 Experimental Parameters..............................71
4.2 Clock Routing........................................73
4.2.1 GMA and SGMA.......................................74
4.2.1.1 Performance......................................76
4.2.1.2 Area and Power...................................76
4.2.1.3 Layer Usage and Via Counts.......................77
4.2.1.4 Executive Time...................................78
4.2.2 Locating Tapping Points............................78
4.2.2.1 Performance......................................79
4.2.2.2 Area and Power...................................80
4.2.2.3 Layer Usage and Via Counts.......................81
4.2.2.4 Executive Time...................................82
4.2.3 Different Architectures............................83
4.2.3.1 Performance......................................85
4.2.3.2 Area and Power...................................86
4.2.3.3 Layer Usage and Via Counts.......................89
4.2.3.4 Executive Time...................................92
4.2.4 Related Figures of Clock Routing...................93
4.3 Layer Assignment.....................................95
4.3.1 Error Wires and OPE Wires..........................99
4.3.2 Layer Usage and Via Issues........................101
4.3.3 Executive Time....................................103
4.3.4 T-junction in the Tapping Point...................104
4.3.5 Related Figures in Layer Assignment...............105
Chapter 5 CONCLUSION AND FUTURE WORK....................127
5.1 Conclusion..........................................127
5.2 Future work.........................................127
REFERENCES..............................................129

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