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研究生:楊盛惟
研究生(外文):Sheng-Wei Yang
論文名稱:應用於數位音頻系統之微功率開關電容三階三角積分調變器設計
論文名稱(外文):Design of Micropower Switched-Capacitor Third-Order Sigma-Delta Modulator for Digital Audio Applications
指導教授:黃育賢陳建中陳建中引用關係
口試委員:郭建宏李文達
口試日期:2007-06-29
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦與通訊研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:100
中文關鍵詞:三角積分調變器低電壓微功率信號與雜訊失真比動態範圍
外文關鍵詞:Sigma-Delta ModulatorLow-VoltageMicropowerSignal-to-Noise-plus-Distortion-Ratio (SNDR)Dynamic Range (DR)
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隨著現今行動電子產品的發展及需求日漸成長,主要著重設計輕薄、電池能維持較長的工作時間,以及提供高的品質,如手機、MP3等可攜式的產品。在可攜式的產品中,電池的重量及大小常是造成產品重量以及大小的關鍵,因此減低功率消耗可以有效減少電池的個數以及電池的壽命。而這類的產品上,軟體與硬體大多都是以數位方式去實現,因此需要一個高解析度、低功率消耗且面積小的類比數位轉換器。為達到上述特點,三角積分調變器扮演了一個很重要角色。
本論文設計一個低電壓/微功率三階三角積分調變器,可應用於數位音頻系統上。為了可攜性的考量,因此本調變器使用單端電源為1.5V,可有效降低電池重量,適合用於有輕便性需求的產品上,且本調變器總耗電量僅788μW,能有效的增加電池使用壽命。由於低電壓系統設計,使得CMOS傳輸閘開關無法正常的導通或關閉,因此,一般低電壓的電路設計亦會在此介紹。在調變器電路的實現上,我們採用全差動式開關電容電路,並以TSMC 0.35μm Mixed-Signal 2P4M製程參數進行模擬,整體佈局面積為1.128 x 1.128 mm2(含I/O PAD)。在超取樣率為64,信號頻寬為20kHz時,所得到的最大信號與雜訊失真比為81.4dB,有效解析度為13.23 bits,動態範圍為80.2dB。
In response to the increasing demands for greater mobility and more powerful functions, design of portable electronic devices are moving toward smaller size, slimmer body, lighter weight, longer battery life, and greater efficiency, such as cellular phones, mp3 players…etc. The weight and size of a portable device, however, is determined to a great extent by the batteries it uses. Therefore, to achieve smaller size and lighter weight, the number of batteries should be reduced, and this can be done by decreasing the chip’s power consumption. Since most of today’s portable devices rely on digital circuits in terms of both software and hardware, an analog-to-digital converter (ADC) is needed. The thesis accordingly designs a sigma-delta modulator (SDM) capable of obtaining high resolution to serve as an improved ADC.
This thesis presents a low-voltage micropower 3rd-order sigma-delta modulator for digital audio applications. For reducing the weight of battery to facilitate the design of smaller and lighter portable products, the proposed modulator uses only a single-end power supply of 1.5V. Moreover, the modulator reports a power consumption as low as 788μW, making it more capable of extending battery life. As a low voltage system is used, the switch driving problem in circuit design is also discussed. The modulator is implemented with a fully-differential switched capacitor (SC) circuit and simulated with the parameters of the TSMC 0.35μm CMOS 2P4M process. With a chip area of 1.128 x 1.128 mm2, the post-simulation results show the modulator capable of achieving a peak SNDR of 81.4dB and a dynamic range of 80.2dB at an oversampling ratio of 64 within a signal bandwidth of 20kHz. The resolution produced reaches 13.23 bits.
中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii

第一章 緒論 1
1.1 相關研究發展近況 1
1.2 研究動機 4
1.3 研究目的 5
1.4 論文架構 6

第二章 三角積分調變器之原理與架構 7
2.1 類比數位之脈波編碼調變轉換方式 7
2.2 超取樣類比數位轉換器之簡介 8
2.3 超取樣類比數位轉換器之原理 9
2.3.1 奈奎氏取樣定理 9
2.3.2 量化誤差 10
2.3.3 超取樣原理與優點 14
2.3.4 雜訊移頻 19
2.4 三角積分調變器之架構 22
2.4.1 一階三角積分調變器 22
2.4.2 二階三角積分調變器 24
2.4.3 高階單迴路單位元三角積分調變器 26
2.4.4 多級串接三角積分調變器 28
2.4.5 多位元三角積分調變器 30
2.4.6 三角積分調變器之架構總結 31
2.5 類比數位轉換器效能參數之定義 32

第三章 系統設計與模擬 34
3.1 系統設計流程 35
3.2 整個調變器之系統架構設計與考量 36
3.3 系統行為模擬 37

第四章 微功率開關電容三階三角積分調變器 44
4.1 低電壓下開關電容積分器之限制因素 44
4.2 低電壓下開關電容積分器之設計 47
4.2.1 低臨界電壓製程 47
4.2.2 倍壓電路 47
4.2.3 靴帶式開關電路 49
4.2.4 開關式運算放大器電路 50
4.2.5 總結 50
4.3 系統子電路設計與模擬 52
4.3.1 運算放大器 52
4.3.2 偏壓電路 57
4.3.3 共模回授電路 60
4.3.4 開關電容積分器電路 60
4.3.5 一位元比較器 63
4.3.6 非重疊時脈電路 65
4.3.7 時脈倍壓電路 66
4.3.8 數位類比轉換器 69
4.3.9 積分器回授電路 70
4.4 開關電容三階三角積分調變器佈局前之模擬結果 72
4.5 混合信號電路佈局考量 77
4.6 晶片實現 80
4.7 開關電容三階三角積分調變器佈局後之模擬結果 81
4.8 應用在數位音頻系統之三角積分調變器比較 85

第五章 量測 86
5.1 量測環境與方法 86
5.1.1 雜訊隔離電路 88
5.1.2 電源穩壓電路 89
5.1.3 差動信號產生器 90
5.2 量測結果 91

第六章 結論與未來研究方向 95
6.1 結論 95
6.2 未來研究方向 96

參考文獻 97
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