臺灣博碩士論文加值系統

第二代通用串列匯流排(Universal Serial Bus, USB2.0)已經被廣泛的應用在個人電腦及其週邊設備上，究其受歡迎的原因，即其能容許多種的周邊裝置同時接上且即插即用，且具有熱插拔性，和裝置無需外接電源等多項優點，但最重要的是資料傳輸率可達480Mbps，如此大量的傳輸速度是USB1.1 (12Mbps) 的40倍以上，並且具有向下相容USB1.1(全速、低速)的特性。
本篇論文主要內容，為設計一個應用於USB2.0高速模式之傳輸器及其所需的能隙電壓參考源 (Bandgap Voltage Reference)產生器。能隙電壓參考源主要是設計一個電路，藉由正比於溫度的電路(PTAT)去補償雙載子電晶體所產生的負溫度係數，以產生一個能夠不因電源電壓以及溫度的變化而產生太大變動的參考電壓，以提升整個電路的準確度、可靠度及良率。再針對高速傳輸的標準製作了一個應用於高速模式(480Mbps)頻寬的傳輸器，並且利用 HSPICE模擬軟體工具搭配 TSMC 0.18um CMOS 元件模型來進行電路的模擬及分析，電源電壓主要採用3.3V搭配1.8V，訊號來源取自數位電路，消耗功率為115.52mW。最後透過高速、全速和低速驅動器將訊號輸出到匯流排上，完成整個傳輸器的功能。

For the interface of multimedia data between personal computers and peripheral components, the Universal Serial Bus 2.0 (USB2.0) technology is now being widely used. For the popular reason, USB2.0 can permit several types of peripheral devices to connect and use simultaneously at the same time, such as hot “Plug and Play” capability, and no extra power needed and so on. In fact, the most important thing is that the internal bandwidth has been increased to achieve higher data transfer rate (480Mbps). It is 40 times of the USB1.1 (12Mbps) data rate, and USB2.0 can support high, full and low speed date rates.
The objective of this thesis is to design a USB2.0 high-speed transmitter and bandgap voltage reference that is needed by USB2.0 circuit. The bandgap voltage reference generator is to design a circuit that utilizes a PTAT (proportional to absolute temperature) to compensate the negative temperature coefficient resulting from BJT. In addition, it is very important to generate a power supply voltage and temperature independent reference voltage to improve the performance of circuits such as accuracy, reliability and yield rate. Furthermore, the transceiver architecture and transmitter circuit are proposed for USB2.0 high-speed mode with 480Mbps bandwidth. The circuit is simulated by HSPICE using TSMC 0.18um CMOS 1P5M process models. Power supply is 3.3V and 1.8V, and the total power consumption at the supply voltage 3.3V is 115.52mW. The HS (High-Speed), FS (Full Speed) and LS (Low Speed) transmitters drive the serial data on to the bus.

CONTENTS
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 USB2.0 Overview 2
1.2.1 Goals for the Universal Serial Bus 2
1.2.2 Taxonomy of Application Space 3
1.2.3 Feature List 4
1.3 Organization of the Thesis 6
CHAPTER 2 THE ARCHITECTURAL OVERVIEW OF USB2.0 7
2.1 USB System Description 7
2.1.1 Bus Topology 8
2.1.2 USB Host 9
2.1.3 USB Devices 9
2.2 Physical Interface 11
2.3 Bus Protocol 13
2.4 Robustness 14
2.5 System Configuration 14
2.5.1 Attachment of USB Devices 14
2.5.2 Removal of USB Devices 15
2.5.3 Bus Enumeration 15
2.5.4 USB Host: Hardware and Software 15
2.6 Data Encoding/Decoding 16
2.6.1 NRZI Data Encoding 16
2.6.1 Bit Stuffing 17
CHAPTER 3 BANDGAP REFERENCE FOR USB2.0 TRANSCEIVER 18
3.1 Introduction 18
3.2 Supply-Independent Biasing 19
3.3 Temperature-Independent Reference 21
3.3.1 Negative-TC Voltage 21
3.3.2 Positive-TC Voltage 23
3.3.3 Bandgap Reference 26
3.3.4 Current Reference Generator 27
3.4 Circuit Realization 28
3.4.1 BGR Core Design 29
3.4.2 Current Reference Generator Design 30
3.4.3 Voltage Reference Divider Design 31
3.5 Simulation Results 32
CHAPTER 4 THE USB 2.0 TRANSMITTER 35
4.1 The Architecture of Transceiver for USB 2.0 35
4.2 The Circuit Design of the Transmitter 38
4.2.1 High Speed (HS) Transmitter and Current Source 38
4.2.2 Full Speed / Low Speed (FS/LS) Transmitter 44
4.2.3 Pseudo Random Bit Sequence (PRBS) Generator 48
4.2.4 Status Controller 50
4.3 Summary 53
4.3.1 High-Speed Mode 53
4.3.2 Full-Speed Mode 58
4.3.3 Low-Speed Mode 60
4.3.4 The Test Configuration 63
CHAPTER 5 CONCLUSIONS 64
REFERENCES 67

REFERENCES
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