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研究生:陳信助
研究生(外文):Hsin-Chu Chen
論文名稱:嵌入式系統中使用預測模式在集合關聯式快取記憶體的省能設計
論文名稱(外文):The Design of Way-Prediction Scheme in Set-Associative Cache for Energy Efficient Embedded System
指導教授:曾嘉影
指導教授(外文):Chia-Ying Tseng
口試委員:曾嘉影
口試委員(外文):Chia-Ying Tseng
口試日期:2008-07-03
學位類別:碩士
校院名稱:大同大學
系所名稱:資訊工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:95
語文別:英文
論文頁數:42
中文關鍵詞:快取記憶體嵌入式系統預測模式
外文關鍵詞:way-predictioncacheembedded system
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嵌入式系統蓬勃發展,功能日趨複雜化,多煤體應用的需求日益增加,相對隨著功能的增加及工作速度的提昇,其所消耗電量也跟著大幅上升。因此有效提高待機時間將是一個很重要的研究方案,研究發現快取記憶體的耗電量佔整體微處理器電量42%,利用預測模式與LRU演算法來提高快取記憶命中率且減少標籤比較次數,因而節省電量消耗。
在本論文中我們利用MRU表格紀錄每一個索引最常被使用區塊來提高快取記憶命中率,並使用MPLRU演算法來降低硬體複雜度和快取記憶體失誤率。實驗顯示我們預測命中率高達90.85%,而節省65.12%電能,實驗結果使用Wattch 模擬器執行SPEC95 benchmarks。
Embedded System develops rapidly, functions turn into more complicate, and multi-media applications are growing daily and they consume more electrical power. Therefore, how to improve stand-by time will become a very important issue. Related researches indicate that the power consumption of processor cache is accounted for a big proportion. Way-prediction and LRU (Least Recently Used) algorithms improve hit rate and would help in reducing the number of tag comparisons, and therefore save energy consumption.
In this thesis, we use MRU (Most Recently Used) table to record the most used block for each index and use Modified Pseudo LRU (MPLRU) Replacement algorithm for reducing hardware complexity and cache miss rate.
Experiments show our prediction hit rate reach 90.15%, thus save 64.12% energy. The experimental results are obtained by using Wattch cache simulator for SPEC95 benchmarks.
ACKNOWLEDGMENTS
ABSTRACT
摘要
TABLE OF CONTENTS
LIST OF FIGURES
LIST OF TABLES
CHAPTER 1 INTRODUCTION
1.1 Introduction
1.2 Motivation and Objectives
CHAPTER 2 BACKGROUND
2.1 Activity between cache and memory
2.1.1 Blocks are placed in a cache
2.1.2 Blocks found if it is in the cache
2.1.3 Block should be replaced on a cache miss
2.1.4 Cache activity happens on a write
2.2 Reducing Cache Miss Penalty
2.2.1 Multi-Level Caches
2.2.2 Critical Word First and Early Restart
2.2.3 Giving Priority to Read Misses over Writes
2.2.4 Merging Write Buffer
2.2.5 Victim Caches
2.3 Reducing Miss Rate
2.3.1 Larger Block Size
2.3.2 Larger Caches
2.3.3 Higher Set-associative
2.3.4 Compiler Optimizations
CHAPTER 3 PROPOSED METHOD
3.1 Conventional Cache Architecture
3.2 Least Recently Used Algorithm
3.3 Proposed Method
CHAPTER 4 EXPERIMENTAL RESULT
4.1 SimpleScalar
4.2 SimpleScalar Simulation Result
4.3 Wattch
CHAPTER 5 WAY PREDICTION ENERGY SAVING
CHPATER 6 CONCLUSION AND FUTURE
REFERENCES
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[7] http://www.simplescalar.com
[8] http://www.eecs.harvard.edu/~dbrooks
[9] Su, C L., and Despain, A. M, “Cache Design Trade-offs for Power and Performance Optimization: A Case study,” Proc. of the 1995 International Symposium on Low Power Design, pp69-74, Apr. 1995
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[12] Biju K Raveendran , T S B Sudarshan , Avinash Patil, Komal Randive, S Gurnaray,
"Predictive Placement Scheme in Set-Associative Cache for Energy Efficient Embedded System", Proceedings of the International Conference of Signal Processing, Communications, and Networking 2008.
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