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研究生:呂文宏
研究生(外文):Wen-Hung Liu
論文名稱:低誤差低功率的列越過和行越過固定長度乘法器設計
論文名稱(外文):DESIGN OF LOW-ERROR AND LOW-POWER FIXED-WIDTH MULTIPLIERS BASED ON ROW-BYPASSING AND COLUMN-BYPASSING
指導教授:汪順祥
指導教授(外文):Shuenn-Shyang Wang
學位類別:碩士
校院名稱:大同大學
系所名稱:通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:29
中文關鍵詞:列越過行越過固定長度乘法器
外文關鍵詞:row-bypassingcolumn-bypassingfixed-width multiplier
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最近幾年來功率的處理在VLSI設計裡受到重要的關注,本論文將主要的目標放在改善乘法器的設計,在根據動態功率損耗的公式,我們針對乘法器裡狀態的轉換或是切換來達到減少功率的損耗。在這篇論文裡我們提出了兩種低功率固定長度乘法器的捨去誤差的補償方法來讓我們的輸入和輸出達到相同的位元數。針對現有的row-bypassing和column-bypassing的乘法器架構,當跳過某幾個row或column時,狀態的轉換或是切換的功率就會降低。捨去位數的部份進位位元由數個AND閘和OR閘產生,換句話說有兩個n個位元的輸入,那麼固定長度的乘法器會產生n個低誤差乘積的位元,但是功率會比標準的平行乘法器低。設計的實現是使用TSMC 0.35 2P4M CMOS製程,乘法器運算速度可以達到100MHz,供應的電壓為3.3伏特,結果顯示功率分別降低了5%和13%並且QSNR提升了10dB。
Power management has become a great concern in VLSI design in recent years, this thesis focuses on the improvement of fixed-width multiplier design, by reducing transition or switch. In this paper we present two methods for designing low power error-compensated fixed-width multipliers which keep the input and the output the same bit width. By applying the row-bypassing structure or column-bypassing structure, the columns or rows are passed, and the switching power will be saved. The truncated part that produces the carry-out bits is replaced with several AND gates and OR gates. In other words, given two n-bit inputs, the fixed-width multipliers generate n-bit products with low product error, but use less power when compared with a standard parallel multiplier. A physical implementation of the proposed design used a standard TSMC 0.35 2P4M CMOS process. The multipliers can operate correctly up to 100MHz and supply voltage is 3.3V. Simulation results show that our method has 5% and 13% power reduction and the QSNR improves 10dB.
CONTENTS

ACKNOWLEDGMENT (in Chinese) I
CHINESE ABSTRACT II
ENGLISH ABSTRACT III
CONTENTS Ⅳ
LIST OF TABLES VI
LIST OF FIGURES VII
CHAPTER 1 INTRODUCTION 1
1.1 Background 1
1.2 Organization of the Thesis 2
CHAPTER 2 REVIEW OF THE DESIGN OF MULTIPLIERS 3
2.1 Parallel Multiplier 3
2.2 Row-Bypassing Multiplier 5
2.3 Column-Bypassing Multiplier 8
CHAPTER 3 PROPOSED FIXED-WIDTH Multiplier 12
3.1 Truncation Fixed-Width Multiplier(Trun-FWM) 12
3.2 Error-Compensated Fixed-Width Multiplier(JKC-FWM) 15
3.3 Proposed Row-Bypassing Fixed-Width Multiplier(RB-FWM) 20
3.4 Proposed Column-Bypassing Fixed-Width Multiplier(CB-FWM) 22
CHAPTER 4 SIMULATION AND RESULTS ANALYSIS 24
4.1 Simulate Environments 24
4.2 Simulation Results 25
CHAPTER 5 CONCLUSIONS 26
5.1 Conclusions 26
REFERENCES 27
[1] Ming-Chen Wen, Sying-Jyan Wang, and Yen-Nan Lin, “Low power parallel multiplier with column bypassing,” IEEE International Symposium on Circuits and Systems, ISCAS, vol. 2, pp.1638-1641, May 2005.
[2] Chang-Young Han, Hyoung-Joon Park, and Lee-Sup Kim, “A low-power array multiplier using separated multiplication technique,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing , Volume 48, Issue 9, pp.866-871, Sept. 2001.
[3] Jongsu Park, San Kim, and Yong-Surk Lee, “A low-power Booth multiplier using novel data partition method,” Proceedings of 2004 IEEE Asia-pacific Conference on Advanced System Integrated Circuits 2004, pp.54-57, Aug. 2004.
[4] Jun-ni Ohban, Vasily G.. Moshnyaga, and Koji Inoue, “Multiplier energy reduction through bypassing of partial products,” 2002 Asia –Pacific Conference on Circuits and Systems (APCCAS ’02), vol. 2, pp.13-17, Oct. 2002.
[5] Chua-Chin Wang, and Gang-Neng Sung, “A low-power 2D bypassing multiplier using 0.35 /spl mu/m CMOS technology,” IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Volume 00, Page(s):4 pp., March 2006.
[6] Jer Min Jou, Shiann Rong Kuang, and Ren Der Chen, “Design of low-error fixed-width multipliers for DSP applications,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume 46, Issue 6, pp.836-842, June 1999.
[7] Sang-Min Kim, Jin-Gyun Chung, and Keshab K. Parhi, “Design of low error CSD fixed-width multiplier,” IEEE International Symposium on Circuits and Systems, ISCAS, Volume 1, pp.1-69-1-72, May 2002.
[8] Hong-An Huang, Yen-Chin Liao, and Hsie-Chia Chang, “A self-compensation fixed-width booth multiplier and its 128-point FFT applications,” IEEE International Symposium on Circuits and Systems, ISCAS, Page(s):4 pp., May 2006.
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