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研究生:李梅禎
研究生(外文):Mei-Chen Li
論文名稱:設計一類似標準函式庫之結構化客製晶片的基本單元
論文名稱(外文):Standard Cell Like Via-Configurable Logic Block Design for Structured ASICs
指導教授:林榮彬林榮彬引用關係
指導教授(外文):Rung-Bin Lin
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:32
中文關鍵詞:結構化客製晶片標準函式庫基本單元
外文關鍵詞:Structured ASICRegular fabricvia configurablecell library
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目前受歡迎的IC 設計方法,ASIC和FPGA,正面臨一項大的挑戰︰ 取得在光罩費用和性能之間的適當平衡。可結構化客製晶片保留ASIC設計的一些特性,例如高效能和使用更小的面積以及擁有FPGA的一些特性,例如低的NRE費用和重複配置來完成設計之功能。可結構化客製晶片由一些預製的電晶體,事先定義完成的金屬層,以及尚未定義的via 層(或少許的金屬層)組成。尚未定義的via 層是留給使用者來連接基本邏輯單元間的連線及基本邏輯單元內的電晶體連線。基本邏輯單元由基本單元組成。一個好的基本單元必須要有高電晶體使用率且可符合各種不同需求的設計。以此基本單元設計晶片時,若能減少設計晶片的開發工具更為重要。在這篇論文裡,我們設計一類似於標準函式庫之基本單元(VCLB)能夠運用現有的標準流程工具進行新晶片設計。我們以此基本單元建立函式庫並介紹運用此基本架構之晶片設計流程。運用我們的基本單元設計之電路在電路時間延遲上可達到用業界標準函式庫所得到的1.34倍且只多出278%的晶片面積。
The popular IC design styles, standard cell design and FPGA, are facing a big challenge: attaining a proper balance between mask cost and performance. Structured ASIC retains some properties of standard cell designs such as higher performance and smaller area and also possesses some properties of FPGA such as low non-recurring engineering cost and re-configurability. It emerges as a good solution to the above challenge. A structured ASIC consists of some prefabricated transistors, prefabricated masks for some metal layers, and a couple of un-customized masks for vias (sometimes metal layers). A base block for structured ASICs must provide powerful functional expression, high integration density, and flexibility to meet various application requirements. Moreover, it should also minimize the efforts of developing tools for chip designs. In this thesis, we propose a standard cell like VCLB that can leverage existing standard cell design tools to perform chip designs using our VCLBs. We create a standard cell library based on our VCLB and perform chip designs using this cell library. Experimental results show that the designs using the cells in our library achieve a delay of 1.34 times that attained by the designs using a commercial standard cell library at the expense of 278% increase in chip area.
List of Figures ix
List of Tables x
Chapter 1. Introduction 1
1.1. Background 1
1.2. Scope of The Work 3
1.3. Thesis Organization 3
Chapter 2. Related Work 4
2.1. Existing VCLBs 4
2.2. Via Configurable Gate Array (VCGA) 5
2.2.1. Via Configurable Function Cell (VCC) 5
2.2.2. Via Configurable Inverter Array (INV) 8
2.3. Drawbacks of Existing VCLBs 10
Chapter 3. Proposed VCLBs 12
3.1. VCLB 12
3.2. Via Configuations 14
3.2.1. Combinational Cells 14
3.2.2. Sequential Cells 15
3.2.3. Cells with Different driving abilities 15
3.2.4. Multi-Function Packed Block(MFPB) 16
Chapter 4. Design Methodology 17
4.1. Cell Library Creation 17
4.2. Standard Cell Design Flow 18
Chapter 5. Experiment Results 19
Chapter 6. Conclusions and Future Work 23
References 24
Appendix A. Cell Library 26
A.1. Table of cells in 5-VCLB cell library 26
A.2. Table of cells in 7-VCLB cell library 29
[1] Zvi Or-bach, “Paradigm Shift in ASIC Technology In-stand Metal Out-stand Cell,” http://www.easic.com.
[2] Behrooz Zahiri, “Structured ASICs: Opportunities and Challenges,” ICCD, pp. 404-409, 2003.
[3] eASIC : The Configurable Logic Company. [Online]. Available:http://www.easic.com/
[4] Kun-Cheng Wu, Yu-Wen Tsai, “Structured ASIC, Evolution or Revolution?, “ISPD, pp.103-106, 2004.
[5] Chien-Chung Lai, “Standard Cell Like Design Flow for Structured ASICs,” M. Eng. Thesis, Yuan Ze Institute of Technology, Taiwan, R.O.C. July 2007.
[6] N. Jayakumar and S. P. Khatri, “A Metal and Via Maskset Programmable VLSI Design Methodology using PLAs,” ICCD, 2004, pp. 590–594.
[7] B. Hu, H. Jiang, Q. Liu, and M. Marek-Sadowska, “Synthesis and Placement Flow for Gain-Based Programmable Regular Fabrics,” ISPD, 2003, pp. 197–203.
[8] C. Patel, A. Cozzie, H. Schmit, and L. Pileggi, “An Architectural Exploration of Via Patterned Gate Arrays,” ISPD, 2003, pp. 184–189.
[9] N. V. Shenoy, J. Kawa, R. Camposano, “Design Automation for Mask Programmable Fabrics,” DAC, 2004, pp. 192-197.
[10] Yajun Ran and Malgorzata Marek-Sadowska, "Designing Via-Configurable Logic Blocks for Regular Fabric", IEEE Transactions on VLSI Systems, VOL. 14, NO. 1, JANUARY 2006.
[11] Z. A. Lomnicki, “Two-Terminal Series-Parallel Networks,” Adv. in Appl. Prob., 4(1):109–150, April 1972.
[12] Yajun Ran and Malgorzata Marek-Sadowska, “The Magic of A Via-Configurable Regular Fabric,” ICCD, 2004, pp. 338–343.
[13] Shu-Ren Ker, “An Automatic Library Development System,” M. Eng. Thesis, Yuan Ze Institute of Technology, Taiwan, R.O.C. June 2000.
[14] Deepak D. Sherlekar, “Design Considerations for Regular Fabrics,” ISPD, April 18-21,2004, pp.97-102.
[15] L.Pileggi, H.Schmit, A.J.Strojwas, P.Gopalakrishnan, V.Kheterpal, A.Koorapaty, C.Patel,V.Rovner, K.Y.Tong, “Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off,”DAC, 2003, pp. 782-787.
[16] Takumi Okamoto, Tsutomu Kimoto, Naotaka Maeda, “Design Methodology and Tools for NEC Electronics’Structured ASIC ISSP,” ISPD, 2004, pp.90-96.
[17] R. Reed Taylor, Herman Schmit, “Creating a Power-Aware Structured ASIC,” ISLPED’04, August 9–11, 2004, pp.74-77.
[18] V. Kheterpal, V. Rovner, T.G. Hersan, D. Motiani, Y. Takegawa, A.J. Strojwas, L. Pileggi, “Design Methodology for IC Manufacturability Based on Regular Logic-Bricks,” DAC, 2005, pp.192-197.
[19] Kim Yaw Tong, Vyacheslav Rovner, Lawrence T. Pileggi, and Veerbhan Kheterpal, “Design Methodology of Regular Logic Bricks for Robust Integrated Circuits,” ICCD, 2006.
[20] R. Reed Taylor, Herman Schmit, “Enabling Energy Efficiency in Via-Patterned Gate Array Devices,” DAC, 2004, pp. 874-877.
[21] A. Koorapaty, V. Kheterpal, P. Gopalakrishnan, M. Fu, L. Pileggi, “Exploring Logic Block Granularity for Regular Fabrics,” DATE, 2004
[22] Aneesh Koorapaty, Lawrence Pileggi, and Herman Schmit, “Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics,” LNCS 2778, 2003, pp. 426–436.
[23] L. Macciarulo, C. F. Caccamo, D. Pandini, “A Comparison between Mask- and
Field-programmable Routing Structures on Industrial FPGA Architectures,”GLSVLSI, 2004, pp.436-439.
[24] Veredas, F.-J.; Scheppler, M.; Pfleiderer, H.-J, “Automated Conversion from a LUT-based FPGA to a LUT-based MPGA with Fast Turnaround Time,” DATE, 2006, pp. 36-41.
[25] Mike Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo, “A Methodology for FPGA to Structured-ASIC Synthesis and Verification,” DATE, 2006, pp. 64-69.
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