目前受歡迎的IC 設計方法，ASIC和FPGA，正面臨一項大的挑戰︰ 取得在光罩費用和性能之間的適當平衡。可結構化客製晶片保留ASIC設計的一些特性，例如高效能和使用更小的面積以及擁有FPGA的一些特性，例如低的NRE費用和重複配置來完成設計之功能。可結構化客製晶片由一些預製的電晶體，事先定義完成的金屬層，以及尚未定義的via 層（或少許的金屬層）組成。尚未定義的via 層是留給使用者來連接基本邏輯單元間的連線及基本邏輯單元內的電晶體連線。基本邏輯單元由基本單元組成。一個好的基本單元必須要有高電晶體使用率且可符合各種不同需求的設計。以此基本單元設計晶片時，若能減少設計晶片的開發工具更為重要。在這篇論文裡，我們設計一類似於標準函式庫之基本單元（VCLB）能夠運用現有的標準流程工具進行新晶片設計。我們以此基本單元建立函式庫並介紹運用此基本架構之晶片設計流程。運用我們的基本單元設計之電路在電路時間延遲上可達到用業界標準函式庫所得到的1.34倍且只多出278%的晶片面積。

The popular IC design styles, standard cell design and FPGA, are facing a big challenge: attaining a proper balance between mask cost and performance. Structured ASIC retains some properties of standard cell designs such as higher performance and smaller area and also possesses some properties of FPGA such as low non-recurring engineering cost and re-configurability. It emerges as a good solution to the above challenge. A structured ASIC consists of some prefabricated transistors, prefabricated masks for some metal layers, and a couple of un-customized masks for vias (sometimes metal layers). A base block for structured ASICs must provide powerful functional expression, high integration density, and flexibility to meet various application requirements. Moreover, it should also minimize the efforts of developing tools for chip designs. In this thesis, we propose a standard cell like VCLB that can leverage existing standard cell design tools to perform chip designs using our VCLBs. We create a standard cell library based on our VCLB and perform chip designs using this cell library. Experimental results show that the designs using the cells in our library achieve a delay of 1.34 times that attained by the designs using a commercial standard cell library at the expense of 278% increase in chip area.

List of Figures ix
List of Tables x
Chapter 1. Introduction 1
1.1. Background 1
1.2. Scope of The Work 3
1.3. Thesis Organization 3
Chapter 2. Related Work 4
2.1. Existing VCLBs 4
2.2. Via Configurable Gate Array (VCGA) 5
2.2.1. Via Configurable Function Cell (VCC) 5
2.2.2. Via Configurable Inverter Array (INV) 8
2.3. Drawbacks of Existing VCLBs 10
Chapter 3. Proposed VCLBs 12
3.1. VCLB 12
3.2. Via Configuations 14
3.2.1. Combinational Cells 14
3.2.2. Sequential Cells 15
3.2.3. Cells with Different driving abilities 15
3.2.4. Multi-Function Packed Block(MFPB) 16
Chapter 4. Design Methodology 17
4.1. Cell Library Creation 17
4.2. Standard Cell Design Flow 18
Chapter 5. Experiment Results 19
Chapter 6. Conclusions and Future Work 23
References 24
Appendix A. Cell Library 26
A.1. Table of cells in 5-VCLB cell library 26
A.2. Table of cells in 7-VCLB cell library 29

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