臺灣博碩士論文加值系統

本論文設計應用於3.5-GHz直接降頻接收架構的CMOS偶次諧波混頻器與八相位壓控振盪器晶片。第一顆晶片為無電感偶次諧波混頻器，利用源極低輸入阻抗方式解決傳統閘極高輸入阻抗不易匹配的問題，選擇適當MOS電晶體的尺寸，在不需製程電感使用下達到匹配電路，節省晶片面積。量測結果，射頻訊號為3.5 GHz和中頻為10 MHz時，在本地振盪訊號必v為-3 dBm的驅動下，電壓轉換增益為15.3 dB，輸入第三階截止點為0.1 dBm，輸入第二階截止點為28.7 dBm。供應電壓為1.8 V，電路動態必v消耗為5.7 mW。此晶片與文獻所提出的架構比較，其佔據較小的佈局面積，僅為0.634 mm2。
第二顆晶片為可變增益I/Q偶次諧波混頻器，以PMOS電晶體取代共模回授負載的回授電阻，其操作於深三極管區當作一線性電阻來改變負載阻抗，進而達成可變轉換增益。其特點是既不影響射頻埠阻抗匹配，亦不造成整體電流的變動而影響線性度。I/Q兩路共用射頻轉導級，並利用電容交互耦合技術來提高轉換增益。量測結果，射頻訊號為3.5 GHz和中頻為10 MHz時，在本地振盪訊號必v為0 dBm的驅動下，可變轉換增益範圍為1至13 dB，輸入第三階截止點為-0.2至1.1 dBm。供應電壓為1.8 V，電路動態必v消耗為3.61 mW。此晶片與文獻比較提供了1至13 dB可變轉換增益的特性，並能維持良好的線性度表現。
最後一顆晶片為運用疊接耦合技術之八相位壓控振盪器，利用四組互補式交互耦合對壓控振盪器互相鎖定產生45°相位差的八相位振盪訊號輸出，並運用疊接耦合技術來降低由大訊號織T使電晶體進入三極管區時的負載效應，因此降低相位雜訊。以量測結果，振盪頻率為1.5至2.0 GHz，輸出必v為-0.8至1.6 dBm，相位雜訊在距離輸出振盪頻率1 MHz處為-120.9至-129.3 dBc/Hz。相位誤差為3.6°，振幅誤差為±35 mV，即輸出必v誤差為±0.94 dB。核心壓控振盪器每組必v消耗為4.5 mW。與文獻比較，此晶片有較寬的可調頻寬與較低的相位雜訊表現。

CMOS even-harmonic mixers and octave-phase VCO are designed in this thesis for 3.5-GHz direct-conversion receiver. First, an inductorless even-harmonic mixer was deigned, which utilizes the low-impedance characteristic of MOS source node as the input port to overcome the impedance match difficulty when high-impedance gate node is conventionally used as the input port. Therefore, the input match can be easily achieved by properly selecting the MOS size without using any inductors in the match network and hence the chip size is dramatically reduced. The implemented 0.18-

目錄
目錄
圖目錄
表目錄
第一章 緒論
1.1 研究背景與動機
1.2 論文架構
第二章 直接降頻與偶次諧波直接降頻接收架構
2.1 直接降頻接收架構
2.2 偶次諧波直接降頻接收架構
第三章 CMOS偶次諧波混頻器
3.1 混頻器參數
3.1.1 轉換增益
3.1.2 雜訊指數
3.1.3 線性度
3.1.4 隔離度與直流偏移
3.2 無電感偶次諧波混頻器設計
3.2.1 電路架構與分析
3.2.2 設計流程
3.2.3 模擬與量測結果
3.2.4 結果討論
3.3 可變增益I/Q偶次諧波混頻器設計
3.3.1 電路架構與分析
3.3.2 設計流程
3.3.3 模擬與量測結果
3.3.4 結果討論
第四章 CMOS八相位壓控振盪器
4.1 振盪器振盪分析
4.1.1 負阻分析法
4.1.2 阻抗軌跡法
4.2 相位雜訊分析
4.2.1 線性非時變模型
4.2.2 線性時變模型
4.3 運用疊接耦合技術之八相位壓控振盪器設計
4.3.1 主動埠架構的選擇
4.3.2 電流源對壓控振盪器的影響
4.3.3 電路架構與設計流程
4.3.4 模擬與量測結果
4.3.5 結果討論
第五章 結論
參考文獻

[1] 李建宇、張輝、王彬，無線寬頻存取技術與應用，全華圖書，民國九十六年。
[2] http://ieee802.org/16/
[3] http://www.wimaxforum.org/home/
[4] http://www.wimax.com/
[5] 張盛富、張嘉展，無線通訊射頻晶片模組設計，全華圖書，民國九十六年。
[6] 黃俊穎，應用於WiMAX與第四代行動通訊之CMOS直接升降頻器及數位調控增益放大器設計，國立中正大學電機工程研究所碩士論文，民國九十六年。
[7] B. Razavi, RF Microelectronics, Prentice Hall Publishers USA (1998).
[8] A. A. Abidi, “Direct-Conversion Radio Transceivers for Digital Communications,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 1399 – 1410, Dec. 1995.
[9] Z. Zhang, Z. Chen, and J. Lau, “A 900 MHz CMOS Balanced Harmonic Mixer for Direct Conversion Receivers,” IEEE Radio and Wireless Conf. (RAWCON), Sep. 2000, pp. 219 – 222.
[10] M.-F. Huang, S.-Y. Lee. and C.J. Kuo, “A CMOS Even Harmonic Mixer with Current Reuse For Low Power Applications,” in Proc. ACM Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 2004, pp.290 – 295.
[11] K. Nimmagadda and G. M. Rebeiz, “A 1.9 GHz Double-Balanced Subharmonic Mixer for Direct Conversion Receivers,” IEEE Radio Frequency Integrated Circuits Symposium, May 2001, pp. 253 – 256.
[12] J. Laskar, B. Matinpour, S. Chakraborty, Modern Receiver Front-Ends: Systems, Circuits, and Integration, John Wiley & Sons Publishers, USA, 2004.
[13] K. Leong and R.G. Meyer, “Monolithic RF Active Mixer Design,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 3, pp.231 – 239, March 1999.
[14] 黃敏峰，應用於無線接收器之偶次諧波混頻器設計與實現，國立中正大學電機工程研究所博士論文，民國九十五年。
[15] T. Yamaji and H. Tanimoto, “A 2 GHz Balanced Harmonic Mixer for Direct-Conversion Receivers,” Proc. of IEEE Custom IC Conf., May 1997, pp. 9.6.1 – 9.6.4.
[16] T. Yamaji, H. Tanimoto and H. Kokatsu, “An I/Q Active Balanced Harmonic Mixer with IM2 Cancelers and 45° Phase Shifter,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 2240 – 2246, Dec. 1998.
[17] L. Sheng, J. C. Jensen and L. E. Larson, “A Wide-bandwidth Si/SiGe HBT Direct Conversion Sub-Harmonic Mixer/Downconverter,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1329 – 1337, Sept. 2000.
[18] S. J. Fang, S. T. Lee and D. J. Allstot, “ A 2 GHz CMOS Even Harmonic Mixer for Direct Conversion Receivers,” in proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2002, vol. 4, pp. 807 – 810.
[19] M. Goldfarb, E. Balboni and J. Cavery, “Even Harmonic Double-Balanced Active Mixer for use in Direct Conversion Receivers,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 1762 – 1766, Oct. 2003.
[20] Byoung Gun Choi and Chul Soon Park, “A 5.8 GHz SiGe HBT Direct-Conversion I/Q-Channel Sub-Harmonic Mixer for Low Power and Simplified Receiver Architecture,” IEEE MTT-S International Microwave Symposium, June 2005, pp. 177 – 180.
[21] H.-C. Chen, Tao Wang, S.-S. Lu, and G.-W. Huang, “A Monolithic 5.9-GHz CMOS I/Q Direct-Down Converter Utilizing a Quadrature Coupler and Transformer-Coupled Subharmonic Mixers,” IEEE Microwave and Wireless Components Letters, vol. 16, no. 4, pp. 197 – 199, April 2006.
[22] P. Upadhyaya, M. Rajashekharaiah, Deukhyoun Heo, Y.-J. Emery Chen, “A High IIP2 Doubly Balanced Sub-Harmonic Mixer in 0.25-μm CMOS for 5-GHz ISM Band Direct Conversion Receiver,” IEEE Radio Frequency Integrated Circuits Symposium, June 2005, pp. 175–178.
[23] M.-F. Huang, S.-Y. Lee., and C.J. Kuo, “Design and Analysis of a CMOS Even Harmonic Mixer with Current Reuse Circuits,” in Proc. IEEE Asia-Pacific Conferece on Circuits and Systems (APCCAS 2004), Dec. 2004, pp.269 – 272.
[24] M.-F. Huang, S.-Y. Lee.and C.J. Kuo, “A 5.25 GHz CMOS Even Harmonic Mixer with an Enhancing Inductance,” in Proc. ICCC Int. Symp. Circuits and Systems (ISCAS), May 2005, pp. 2116 – 2119.
[25] S.-Y. Lee, M.-F. Huang and C. J. Kuo, “Analysis and Implementation of A CMOS Even Harmonic Mixer with Current Reuse for Heterodyne/Direct Conversion Receivers,” IEEE Trans. Circuits and Systems I: Regular Paper, vol. 52, pp. 1741 – 1751, Sept. 2005.
[26] M.-F. Huang, C.J. Kuo and S.-Y. Lee, “A 5.25-GHz CMOS Folded-Cascode Even-Harmonic Mixer for Low-Voltage Applications,” IEEE Trans. Microwave Theory and Tech., vol. 54, pp. 660 – 669, Feb. 2006.
[27] Ming-Feng Huang, Chung J. Kuo, “A CMOS Dual Class-AB Technique for Highly Linear Even Harmonic Mixer,” IEEE Asian Solid-State Circuits Conference (ASSCC 2006), Nov. 2006, pp. 367 – 370.
[28] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Publishers, Singapore, 2001.
[29] J.-Y. Hsieh and S.-Y. Lee, “Theoretical Analysis and Implementation of a Variable Gain Even Harmonic Mixer,” IEEE International Symposium on VLSI Design, Automation and Test, April 2007, pp.1 – 4.
[30] T.-H. Wu, C. Meng and T.-H. Wu, “5.7 GHz GaInp/GaAs HBT sub-harmonic Gilbert downconverter with octet-phase LO generator,” IEEE Electronics Letters, vol. 42, Issue 19, pp. 1098 – 1099, Sept. 2006.
[31] R. Point, M. Mendes and W. Foley, “A Differential 2.4GHz Switched-Gain CMOS LNA for 802.11b and Bluetooth,” IEEE Radio and Wireless Conference (RAWCON), Aug. 2002, pp. 221 – 224.
[32] K. L. Fong, “Dual-Band High-Linearity Variable-Gain Low-Noise Amplifiers for Wireless Applications,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 1999, pp. 224 – 225.
[33] T. Cho et al, “A Single-Chip CMOS Direct-Conversion Transceiver for 900 MHz Spread-Spectrum Digital Cordless Phones,” IEEE International Solid-State Circuits Conference, Feb 1999, pp. 228 – 229.
[34] W. Zhuo, S. Embabi, J. Pineda de Gyvez, E. Sánchez-Sinencio, “Using Capacitive Cross-Coupling Technique in RF Low-Noise Amplifiers and Down-Conversion Mixer Design,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2000, pp. 116 – 119.
[35] W. Zhuo, X. Li, S. Shekhar, S. H. K. Embabi, J. Pineda de Gyvez, D. J. Allstot, and E. Sánchez-Sinencio, “A Capacitor Cross-Coupled Common-Gate Low Noise Amplifier,” IEEE Transactions on Circuits and Systems – II: Express Briefs, vol. 52, no. 12, pp. 875 – 879, Dec. 2005.
[36] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier,” IEEE Journal of Solid-State Circuits, vol. 32, no. 5, May 1997.
[37] A. P. S. Khanna and J. Obregon, “Microwave oscillator design,” IEEE Trans. Microwave Theory Tech., vol. 29, no. 6, pp. 606 – 607, June 1981.
[38] B. Van der Pol, “Forced Oscillations in a Circuit with Nonlinear Resistance (Reception with Reactive Triode),” Philosophical Magazine, vol. 3, pp. 65 – 80, Jan. 1927.
[39] R. Kurokawa, “Injection Locking of Microwave Solid-State Oscillators,” Proceedings of IEEE, vol. 61, no. 10, pp. 1386 – 1410, October 1973.
[40] N. M. Nguyen and R. G. Meyer, “Start-up and Frequency Stability in High-Frequency Oscillators,” IEEE Journal of Solid-State Circuits, vol. 27, no. 5, pp. 810 – 819, May 1992.
[41] D. B. Leeson, “A Simplified Model of Feedback Oscillator Noise Spectrum,” Proceedings of the IEEE, vol. 42, Feb. 1965, pp. 329 – 330.
[42] A. Hajimiri, T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp.179 – 194, Feb. 1998.
[43] A. Hajimiri, T. H. Lee, “Corrections to A General Theory of Phase Noise in Electrical Oscillators,” IEEE Journal of Solid-State Circuits, vol. 33, no. 6, pp.928, June 1998.
[44] T. H. Lee, A. Hajimiri, “Oscillator Phase Noise: A Tutorial,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 326 – 336, March 2000.
[45] D. Ham and A. Hajimiri, “Concepts and Methods in Optimization of Integrated LC VCOs,” IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp. 896 – 909, June 2000.
[46] A. Hajimiri, T. H. Lee, “Phase Noise in CMOS Differential LC Oscillators,” Symposium on VLSI Circuirs Digest of Technical Papers, June 1998, pp. 48 – 51.
[47] J. J. Rael, A. A. Abidi, “Physical Processes of Phase Noise in Differential LC Oscillators,” in Proc. IEEE Custom Integrated Circuit conf., May 2000, pp. 569 – 572.
[48] E. Hegazi, H. Sjoland, A A. Abidi, “A Filtering Technique to Lower LC Oscillator Phase Noise,” IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp.1921 – 1930, Dec. 2001.
[49] J.-H. Chang, Y.-S. Youn, M.-Y. Park, C.-K. Kim, “A New 6 GHz fully integrated Low Power Low Phase CMOS LC Quadrature VCO,” IEEE Radio Frequency Integrated Circuits Symposim, June 2003, pp. 295 – 298.
[50] J. H. Chang, C. K. Kim, “A Symmetrical 6-GHz Fully Integrated Cascode Coupling CMOS LC Quadrature VCO,” IEEE Microwave and Wireless Components Letters, vol. 15, no. 10, pp. 670 – 672, Oct. 2005.
[51] P. Andreani, A. Bonfanti, L. Romano, C. Samori, “Analysis and Design of a 1.8-GHz CMOS LC Quadrature VCO,” IEEE Journal of Solid-State Circuits, vol. 37, no. 12, Dec. 2002.
[52] J.-H. Kim, H.-J. Yoo, “Low Power Octave-phase LC VCO for Direct Conversion 5 GHz WLAN Receiver,” IEEE Asia-Pacific Microwave Conference Proceedings, vol 5, Dec. 2005.
[53] L.-C. Cho; C. Lee; S.-I. Liu, “A 1.2-V 37 – 38.5-GHz Eight-Phase Clock Generator in 0.13-μm CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 42, no. 6, pp. 1261 – 1270, June 2007.
[54] D. Axelrad E. de Foucauld, M. Boasis, P. Martin, P. Vincent, M. Belleville, and F. Gaffiot, “A Multi-phase 10 GHz QVCO in CMOS/SOI for 40 Gbits/s SONET OC-768 Clock and Data Recovery Circuit,” IEEE Radio Frequency Integrated Circuits Symposium, June 2005, pp. 573-576.