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研究生:何嘉銘
研究生(外文):Jia-Ming He
論文名稱:管線式類比數位轉換器之低必v技術
論文名稱(外文):Low power techniques for pipelined ADC
指導教授:蔡宗亨蔡宗亨引用關係
指導教授(外文):Tsung-Heng Tsai
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:96
語文別:中文
論文頁數:101
中文關鍵詞:校正應用反相器之電路時脈重新安排依比例減少運算放大器共用管線式類比數位轉換器低必v
外文關鍵詞:Pipelined ADClow poweropamp sharingscaling downtiming rerrangementinverter-based circuitcalibration
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本論文共分為兩部分,在第一個部分方面是設計一個八位元100MHz的管線式類比數位轉換器。而在整個電路中最重要的部分就是低必v,我們將採用數個技術來降低電路的必v消耗。在架構上,我們選用每級2.8位元的架構來減少運算放大器的使用,以減低必v消耗,而且此架構因串聯的級數少,因此引入的雜訊也能相對減少,能有比較高的解析度。此外我們選用了低位移誤差的動態比較器來解決此架構的低校正範圍的問題。接著在電路上我們使用了運算放大器共用與依比例減少的技術,以減少運算放大器的數量及其必v消耗。在此我們也提出了一個方法,我們更改了管線式類比數位轉換器的時脈安排,應用此方法,除了可降低運算放大器的規格需求外,還可去除管線式類比數位轉換器的取樣保持電路。此管線式類比數位轉換器是使用0.18-
This thesis consists of two parts. An 8-bit, 100MHz pipelined ADC was designed in the first part. The goal of this design is to achieve low-power dissipation. Several techniques were investigated to lower the power consumption. In the architecture level design, we used 2.8-bit/stage to reduce the number of operational amplifiers, so as to lower the power consumption. And because of fewer stages in series, the introduced noise would be potentially decreased. We can get higher resolution in this architecture. Besides, we chose a low-offset dynamic comparator to compensate the problem of low correction range in this architecture. In the circuit level design, techniques including operational amplifier sharing and scaling down were employed to further reduce the operational amplifiers. Furthermore, we proposed a new timing arrangement in the pipelined ADC. With this method, we can not only relax the requirement of the operational amplifiers, but also remove the sample and hold of pipelined ADC. This pipelined ADC is implemented in a 0.18-
致謝辭 i
摘要 v
Abstract vi
目錄 viii
圖目錄 xii
表目錄 xvi
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機與目的 1
1.3 論文架構 5
第二章 類比數位轉換器架構與簡介 7
2.1 類比數位轉換器簡介 7
2.1.1 解析度 (Resolution) 8
2.1.2 輸入範圍 (Input Range) 8
2.1.3 訊號雜訊比 (Signal-To-Noise Ratio, SNR) 9
2.1.4 訊號雜訊失真比 (Signal-To-Noise+ Distortion Ratio, SNDR) 11
2.1.5 有效位元 (Effective Number of Bits, ENOB) 11
2.1.6 動態範圍 (Dynamic Range) 12
2.1.7 微分非線性誤差 (Differential Nonlinearity, DNL) 12
2.1.8 積分非線性誤差 (Integral Nonlinearity, INL) 13
2.1.9 位移誤差 (Offset) 14
2.1.10 增益誤差 (Gain Error) 14
2.2 類比數位轉換器架構 15
2.2.1 快取式類比數位轉換器 (Flash ADC) 16
2.2.1.1 Sparkles in Thermometer Code 18
2.2.1.2 Metastability in Flash ADC 19
2.2.2 摺疊內插式類比數位轉換器(Folding and Interpolation) 20
2.2.2.1 摺疊式類比數位轉換器(Folding ADC) 20
2.2.2.2 內插式類比數位轉換器(Interpolation ADC) 21
2.2.3 兩階段式類比數位轉換器 ( Two-Step ADC ) 22
2.2.4 管線式類比數位轉換器 ( Pipelined ADC ) 23
2.2.5 逐漸趨近式類比數位轉換器 (SAR ADC) 25
2.2.6 分時並行式類比數位轉換器 ( Time-Interleaved ADC ) 27
第三章 管線式類比數位轉換器架構與設計 29
3.1 管線式類比數位轉換器簡介 29
3.2 管線式類比數位轉換器架構 31
3.2.1 1.5bit/stage 31
3.2.2 2.8bit/stage 34
3.2.3 比較 35
3.3 時脈產生電路 37
3.4 負載電容及全差動式運算放大器設計 39
3.4.1 取樣電容 40
3.4.2 運算放大器設計 41
3.4.2.1 規格分析 41
3.4.2.2 運算放大器設計 42
3.4.2.3 共模迴授(Common Mode Feedback, CMFB) 44
3.4.2.4 偏壓電路 45
3.4.2.5 模擬結果 46
3.5 取樣保持電路設計 48
3.5.1 開關 48
3.5.2 取樣保持電路 51
3.6 MDAC電路設計 54
3.6.1 MDAC電路運作 54
3.6.2 控制邏輯 56
3.7 類比數位轉換器子電路 56
3.7.1 動態比較器 56
3.7.2 2.8位元ADSC 58
3.7.3 3位元ADSC 59
3.8 數位誤差校正電路與移位暫存器 60
3.9 低必v技術 61
3.9.1 運算放大器共用(Opamp sharing) 61
3.9.2 依比例下降(Scaling down) 63
3.9.3 時脈重新排列 64
3.10 管線式類比數位轉換器模擬結果 66
3.11 電路佈局圖(Layout) 69
3.12 效能比較 70
3.13 結論 71
第四章 應用反相器之管線式類比數位轉換器 73
4.1 應用比較器之管線式類比數位轉換器 73
4.2 應用反相器之管線式類比數位轉換器 75
4.2.1 想法與架構 75
4.2.2 校正技術 77
4.2.3 低必v技術 79
4.2.3.1 2.8bit/stage 80
4.2.3.2 反相器與電流源共用 80
4.2.4 模擬結果 82
4.5 結論 83
第五章 量測結果 85
5.1 量測方法 85
5.1.1 電源調節電路(Power Regulator Circuit) 87
5.1.2 管線式類比數位轉換器測試版 88
5.2 電路封裝及腳位說明 89
5.3 量測結果 91
第六章 結論與未來展望 95
參考文獻 97
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