臺灣博碩士論文加值系統

本論文介紹軟體定義無線電的發展與適用於手機的精簡接收機架構，探討寬帶低雜訊放大器以及混波器的電路設計，並比較連續時間與離散時間的濾波器。數位電路部份則研究加法器和乘法器的低必v電路，最後討論軟體無線電的未來發展。

This thesis introduces the development of software defined radio (SDR) and the compact handset receiver architectures. We investigate wide-band low noise amplifiers (LNA) and current-based mixers. Comparison of continuous-time (CT) and discrete-time filters is carefully undertaken. We also examine low-power digital circuits of adders and multipliers suitable for digital signal processors.

致 謝 I
中 文 摘 要 II
Abstract III
目 錄 IV
圖表目錄 VI
表目錄 X

第 一 章 緒 論 1
1.1 前言 1
1.2 研究動機 1
1.3 論文架構 2
第二章 軟體定義無線電收發機 3
2.1軟體定義無線電收發機架構 3
2.2直接降頻接收機 8
第三章 數位電路 10
3.1 加法器 10
3.2 乘法器 14
3.2.1 Baugh-Wooley有號數乘法器 14
3.2.2改良式Booth乘法器 15
3.3具推進級之隔熱式乘法器 22
3.4使用markovian輸入之乘法器 29
3.5低延遲半位元管線化乘法器 32
第四章 類比前端電路 35
4.1低雜訊放大器 35
4.1.1雜訊指數 35
4.1.2 1dB增益壓縮點 36
4.1.3交互調變失真 36
4.1.4低雜訊放大器電路 37
4.2差動轉導器 41
4.3 混波器 46
4.4運算放大器 51
4.4.1電路設計 54
4-5濾波器 58
第五章 結論. 71
參考文獻 72

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