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研究生:陳敬為
研究生(外文):Jing Wei Chen
論文名稱:高介電常數材料三氧化二釔、五氧化二釔鈦和三氧化二鐿應用在矽-氧-氮-氧-矽形式之記憶體之物性及電性研究
論文名稱(外文):Study of Physical and Electrical Properties of High-k Y2O3 , Y2TiO5, and Yb2O3 dielectrics SONOS-type memory
指導教授:潘同明
指導教授(外文):T. M. Pan
學位類別:碩士
校院名稱:長庚大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
論文頁數:75
中文關鍵詞:高介電常數三氧化二釔五氧化二釔鈦三氧化二鐿記憶體
外文關鍵詞:high-kY2O3Y2TiO5Yb2O3memory
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傳統浮停閘結構的快閃記憶體,當元件的穿隧氧化層厚度小於10奈米時,原本儲存在複晶矽浮停閘的電荷,很容易因為在氧化層的缺陷,形成漏電路徑,造成原本儲存的資料流失。因此SONOS結構的記憶體元件,被提出是可以解決當元件尺寸縮小時,浮停閘結構所面對的問題。傳統SONOS結構的記憶體元件,是使用氮化矽作為電荷陷捕層,在此種結構內,因為電荷是被儲存在分離式的陷捕位置中,故可改善在浮停閘結構中對於資料保存性的問題。但是因為氮化矽與穿隧氧化層之間的導電帶位能差太低,會使得元件的寫入、抹除速度降低,因此使用高介電常數材料作為SONOS結構的陷捕電荷層,目前正被廣泛研究著。再者,為了提升記憶體的特性,我們嘗試使用二氧化矽/氮化矽的穿隧層去增強記憶體的操作速度和資料保存的特性。
在此篇論文中,我們製作了利用高介電常數材料的電荷陷捕層和二氧化矽/氮化矽的穿隧層的快閃記憶體電容。在此實驗中,我們利用了包含三氧化二釔、五氧化二釔鈦和三氧化二鐿等不同高介電常數材料的電荷陷捕層。我們同時也分析了高介電常數材料的電荷陷捕層和二氧化矽/氮化矽穿隧層的快閃記憶體電容的物理和電性特性。我們也在沉積高介電常數材料的電荷陷捕層後利用快速退火的步驟去增加電荷儲存的能力。
在本篇論文的第二章中,我們使用物理氣象沉積法(濺鍍)製作記憶體電容用純釔作為前驅物來製備三氧化二釔薄膜。藉由物理氣象沉積法(濺鍍)在穿隧氧化層上沉積,再經過不同溫度的快速熱退火形成三氧化二釔薄膜作為奈米微晶粒結構的陷捕電荷層。由論文中的物性分析可得知,經過了800度的快速熱退火後,確實已形成了三氧化二釔奈米微晶粒薄膜。而電性方面則顯示出用物理氣象沉積法(濺鍍)沉積的高介電常數材料陷捕電荷層是具有儲存電子的記憶體元件的特性,如:快速的寫入/更大的記憶窗口……等優點。
在本篇論文的第三章中,我們將介紹利用物理氣象沉積法(濺鍍)的方法去製作六氧化二釔鈦的電荷陷捕層和二氧化矽/氮化矽穿隧層的快閃記憶體電容。在經過物理氣象沉積法(濺鍍)後,我們使用快速退火的處理去形成六氧化二釔鈦。同時X光電子能譜議和原子力顯微鏡被用來分析濺鍍上去的薄膜。在電性方面,我們利用電容-電壓的曲線去了解元件的特性。
在本篇論文的第三章中,我們將介紹利用物理氣象沉積法(濺鍍)的方法去製作三氧化二鐿的電荷陷捕層和二氧化矽/氮化矽穿隧層的快閃記憶體電容。在經過物理氣象沉積法(濺鍍)後,我們使用快速退火的處理去形成三氧化二鐿。同時X光電子能譜議和原子力顯微鏡被用來分析濺鍍上去的薄膜。在電性方面,我們利用電容-電壓的曲線去了解元件的特性。
In the traditional floating gate memory structure, when the tunneling oxide scaled down below 10nm, the stored charge in the poly-silicon floating gate may easily leak through the defects in the tunneling oxide. In order to solve the problem of this gate structure, the SONOS structure is proposed. The conventional SONOS memory device used a silicon nitride film as the charge trapping layer. The charge stored in the silicon nitride which is discrete traps and this can improve the data retention problem of the floating gate structure. But in the traditional SONOS memory, the conduction band offset between tunneling oxide and silicon nitride is small and it will slower the program speed and worse retention property. So using high-k dielectrics to replace traditional silicon nitride has been widely studied. Moreover, in order to improve the memory’s properties, we tried to use the SiO2/Si3N4 tunneling layer to enhance the speed and retention property.
In this thesis, we proposed the fabrication of flash memory MIS capacitances with high-k dielectrics as trapping layer and used SiO2/Si3N4 as the tunneling layer. Various different high-k material trapping layers were used in this experiment, including the Y2O3, Y2TiO5 and Yb2O3. We analyzed the physics and electrical properties of the high-k trapping with SiO2/Si3N4 tunneling layer flash memory. We applied RTA process after deposition high-k trapping layer to increase the capability of storage charge and data retention.
In the chapter 2, we used physical vapor deposition sputter method to fabricate memory capacitor with pure yttrium as precursor to deposit Y2O3 thin film. The thin film deposited on the tunneling oxide by sputter method, and followed by various temperature rapid thermal annealing to form Y2O3 nanocrystal thin film as charge trapping layer. From the physical characteristics, the Y2O3 thin film has actually been formed after 800oC rapid thermal annealing. The memory characteristics of the physical vapor deposition sputtered high-k nanocrystal: fast program, larger memory window have been shown from the electrical data.
In Chapter 3, we introduce our experiment to fabricate Flash memory capacitor with SiO2/Si3N4 tunneling layer and Y2TiO5 charge trapping layer using sputtering method. After sputtering, we use RTA treatment to form Y2TiO5. We use X-ray photoelectron spectrometers (XPS) to investigate the chemical composition of Y2TiO5 trapping layer and Atomic force microscopy (AFM) are done to analyze the composition of the sputtered film. The electrical characteristics C-V curve is measured to know the device performance.
In Chapter 4, we introduce our experiment to fabricate Flash memory capacitor with SiO2/Si3N4 tunneling layer and Yb2O3 charge trapping layer using sputtering method. After sputtering, we use RTA treatment to form Yb2O3. We use X-ray photoelectron spectrometers (XPS) to investigate the chemical composition of Yb2O3 trapping layer and Atomic force microscopy (AFM) are done to analyze the composition of the sputtered film. The electrical characteristics C-V curve is measured to know the device performance.
Abstract (Chinese).....................................................................................I
Abstract (English)...................................................................................IV
Contents………………………………………………………………....V
Figure & Table Captions……………………………….……………VIII
Chapter 1 Introduction……………………........................................1
1-1 Evolution of Flash Memory..................................................................1
1-2 Motivation............................................................................................4
1-3 Thesis Organization..............................................................................5

Chapter 2 Physical and Electrical properties of High-k Y2O3 Memory Capacitor .................................................................................10
2-1 Introduction .......................................................................................10
2-2 Experimental.......................................................................................10
2-3 Results and Discussion.......................................................................11
2-3.1 Physical Characteristics.................................................................11
2-3.1.1 Atomic Force Microscopy (AFM) analysis............................11
2-3.1.2 X-ray diffraction (XRD) analysis...........................................12
2-3.1.3 X-ray photoelectron spectroscopy (XPS) analysis………….12
2-3.2 Electrical Characteristics...............................................................13
2-3.2.1 program speed…….................................................................13
2-3.2.2 retention……………………………………………………..14
2-4 Summaries..........................................................................................15

Chapter 3 Physical and Electrical properties of High-k Y2TiO5 Memory Capacitor..................................................................................27
3-1 Introduction .......................................................................................27
3-2 Experimental.......................................................................................27
3-3 Results and Discussion.......................................................................28
3-3.1 Physical Characteristics.................................................................28
3-3.1.1 Atomic Force Microscopy (AFM) analysis............................28
3-3.1.2 X-ray diffraction (XRD) of Y2TiO5 film analysis…...............28
3-3.1.3 X-ray photoelectron spectroscopy (XPS) of Y2TiO5 film analysis……………………………………………………………....29
3-3.2 Electrical Characteristics...............................................................30
3-3.2.1 program speed…….................................................................30
3-3.2.2 retention……………………………………………………..31
3-4 Summaries..........................................................................................32

Chapter 4 Physical and Electrical properties of High-k Yb2O3 Memory Capacitor..................................................................................44
4-1 Introduction .......................................................................................44
4-2 Experimental.......................................................................................44
4-3 Results and Discussion.......................................................................45
4-3.1 Physical Characteristics.................................................................45
4-3.1.1 Atomic Force Microscopy (AFM) analysis............................45
4-3.1.2 X-ray photoelectron spectroscopy (XPS) of Yb2O3 film analysis……………………………………………………………....45
4-3.2 Electrical Characteristics...............................................................46
4-3.2.1 program speed…….................................................................46
4-3.2.2 retention……………………………………………………..47
4-4 Summaries..........................................................................................48

Chapter 5 Conclusions..............................................................................................58
Reference..................................................................................................60



Figure & Table Captions

Chapter 1
Fig. 1: The semiconductor memory tree.
Fig. 2: The floating gate (FG) structure. The polysilicon is used as floating gate for data storage.
Fig. 3: Current-voltage characteristic of a memory device in the erased and programmed state, showing the Vt shift and the memory window.
Fig. 4: The conventional SONOS memory structure. Silicon nitride is used as charge trapping layer.
Fig. 5: The band diagram of nitride- based SONOS memory.
Fig. 6: Band diagram of the tunneling layer at flatbands and under applied bias V

Chapter 2
Fig. 1: The band diagram of Y2O3 memory with SiO2/Si3N4 as the tunneling barrier.
Fig. 2: Process flow and capacitor structure of Y2O3 trapping layer with SiO2/Si3N4 as the tunneling barrier.
Fig. 3: AFM image of Y2O3 film for (a) control sample and (b) annealed at 700 °C (c) 800°C and (d) 900 °C.
Fig. 4: XRD of Y2O3 trapping layer after anneal in N2 ambient for 30s at various temperatures.
Fig. 5: XPS (a) Y 3d (b) O 1s (c) Si 2p and (d) N 1s of Y2O3 films after different annealing temperatures.
Fig. 6: VFB shift of Y2O3 films for (a) as-deposition (b) annealed at 700°C (c) 800°C and (d) 900°C with SiO2/Si3N4 tunneling layer as a function of stress time.
Fig. 7: All conditions stress at (a) 12V and (b) 15V.
Fig. 8: The data retention of the Y2O3 flash memory at (a) room temperature and (b) 85oC.

Chapter 3
Fig. 1: Process flow and capacitor structure of Y2TiO5 trapping layer with SiO2/Si3N4 as the tunneling barrier.
Fig. 2: AFM image of YTixOy film for (a) control sample and (b) annealed at 700 °C (c) 800°C and (d) 900 °C.
Fig. 3: XRD of Y2TiO5 trapping layer after anneal in O2 ambient for 30s at various temperatures.
Fig. 4: XPS (a) Y 3d (b) O 1s (c) Ti 2p (d) Si 2p (e) N 1s of Y2TiO5 films after different annealing temperatures.
Fig. 5: VFB shift of Y2TiO5 films for (a) as-deposition (b) annealed at 700°C (c) 800°C and (d) 900°C with SiO2/Si3N4 tunneling layer as a function of stress time.
Fig. 6: All conditions stress at (a) 12V and (b) 15V.
Fig. 7: The data retention of the Y2TiO5 flash memory at (a) room temperature and (b) 85oC.

Chapter 4
Fig. 1: Process flow and capacitor structure of Yb2O3 trapping layer with SiO2/Si3N4 as the tunneling barrier.
Fig. 2: AFM image of Yb2O3 film for (a) control sample (b) annealed at 700 °C (c) 800°C and (d) 900 °C.
Fig. 3: XPS (a) Yb 4d (b) O 1s (c) Si 2p and (d) N 1s of Yb2O3 films after different annealing temperatures.
Fig. 4: VFB shift of Yb2O3 films for (a) as-deposition (b) annealed at 700°C (c) 800°C and (d) 900°C with SiO2/Si3N4 tunneling layer as a function of stress time.
Fig. 5: All conditions stress at (a) 12V and (b) 15V.
Fig. 6: The data retention of the Yb2O3 flash memory at (a) room temperature and (b) 85oC.
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