(3.238.130.97) 您好!臺灣時間:2021/05/10 13:56
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:張志信
研究生(外文):Chih-Hsin Chang
論文名稱:鉿鍺氧化物電荷補陷層在非揮發性記憶體的應用
論文名稱(外文):Hafnium Germanium Oxide as Trapping Layer for Nonvolatile Memory Application
指導教授:賴朝松
指導教授(外文):C. S. Lai
學位類別:碩士
校院名稱:長庚大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
論文頁數:87
中文關鍵詞:快閃記憶體電荷捕陷層高介電係數
外文關鍵詞:flash memorytrapping layerhigh-k dielectrics
相關次數:
  • 被引用被引用:0
  • 點閱點閱:134
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在這篇論文中利用高介電係數材料作為快閃記憶體的電荷捕陷層,此高介電係數材料是以鉿和鍺金屬共濺鍍形成的氧化鉿鍺層。添加微量鍺半導體在氧化鉿中,可以藉由形成氧化鍺來提高電荷捕抓能力,並提升氧化鉿在快速熱退火下的熱穩定性。
本篇論文中也同時比較此高介電係數電荷捕陷層,在不同穿隧氧化層:二氧化矽和氧化鉿鉭下的電性。經過不同快速退火處理後,氧化鉿鍺快閃記憶體的遲滯並不會隨著快速退火的溫度升高而一直變大。在二氧化矽穿隧氧化層結構的因素是氧化鉿鍺層的隨著快速退火的溫度升高而有結晶現象,在氧化鉿鉭穿隧氧化層結構的因素除了氧化鉿鍺層還必須考慮氧化鉿鉭熱穩定性,我們選用氧化鉿鉭是因為它的高熱穩定性,實驗結果證明氧化鉿鉭在900℃以下確實改善了寫入速度和記憶保存時間。
In this thesis, we proposed the fabrication of flash memory device with high-k dielectrics, the HfGeOx, as trapping layer is formed by co-sputtering with Hf and Ge. The thermal stability and charge storage can be improved by GeOx embedding in HfOx.
In this thesis, we also compared the electrical characteristic of HfGeOx trapping layer with different tunnel dielectrics: SiO2 and HfTaOx. After different rapid thermal annealing temperature, the hysteresis window does not be increased with arising temperature. It is attributed to crystallize phenomenon in HfGeOx layer with high annealing temperature on SiO2 tunnel dielectrics. On the other hand, we must consider thermal stability of HfTaOx tunnel dielectrics. We use HfTaOx tunnel dielectric due to high thermal stability. The program speed and retention time are improved obviously with RTA temperature less than 900℃.
Contents
Acknowledgement……………………………………………………i
Chinese abstract…………………………………………………ii
English abstract…………………………………………………iii
Contents………………………………………………………………iv
Figure Captions……………………………………………………vii
Table Captions……………………………………………………xiii

Chapter 1 Introduction
1-1 General background ……………………………………………1
1.1.1 SONOS nonvolatile memory device………………………2
1.1.2 Advantages of using high-k materials………………2
1-2 Motivation to study high-k material …………………3
1-3 Thesis organization……………………………………………3

Chapter 2 The Characterization of HfGeOx flash memory with SiO2 tunnel dielectrics

2-1 Introduction ………………………………………………………7
2-2 Experiment Procedures…………………………………………7
2-3 Results and Discussion…………………………………………8
2.3.1 X-ray Photoelectron Spectroscopy (XPS) Analysis of HfGeOx………………………………………………………………………8
2.3.2 X-ray diffraction (XRD) Analysis of HfGeOx………9
2.3.3 Memory Effect and Programming Speed…………………10
2.3.4 Data Retention…………………………………………………10
2.3.5 Trapping Charge and Centroid……………………………11
2-4 Summary ………………………………………………………………12

Chapter 3 The Characterization of HfGeOx flash memory with HfTaOx tunneling dielectric

3-1 Introduction ………………………………………………………32
3-2 Experiment Procedures …………………………………………33
3-3 Results and Discussion…………………………………………34
3.3.1 X-ray diffraction (XRD) of HfGeOx and HfTaOx Analysis……………………………………………………………………34
3.3.2 Memory Effect and Programming Speed…………………35
3.3.3 Data Retention…………………………………………………36
3-4 Summary ………………………………………………………………36

Chapter 4 Comparison of SiO2 and HfTaOx tunneling dielectrics

4-1 Introduction…………………………………………………………52
4-2 Experimental Procedures…………………………………………52
4-3 Results and Discussion……………………………………………53
4.3.1 Measurement of barrier heights……………………………53
4-4 Summary…………………………………………………………………55
Chapter 5 Conclusions and Future Works

5-1 Conclusion …………………………………………………………62
5.1.1 HfGeOx as trapping layer with SiO2 tunnel dielectrics …………………………………………………………………………………62
5.1.2 HfGeOx as trapping layer with HfTaOx tunnel dielectrics…………………………………………………………………62
5.1.3 Comparison the memory characterization of HfGeOx flash memory with SiO2 and HfTaOx tunnel dielectrics ………………………………………………………………………………63
5-2 Future work…………………………………………………………63

References ………………………………………………………………67


Figure Captions
Fig.1-1 The structure of the conventional floating gate nonvolatile memory device……………………………………………5
Fig.1-2 The structure of SOHOS nonvolatile memory device…………………………………………………………………………5
Fig.1-3 Energy band diagram during retention in the nitride trap- based memory………………………………………………………6
Fig.1-4 The structure of SOHOS nonvolatile memory device…………………………………………………………………………6
Fig.2-1 The processes flow of HfN/HfO2/HfGeOx/SiO2 structure……………………………………………………………………16
Fig.2-2 XPS of O1s for HfGeOx film after annealing in N2 ambient for 30s at various temperatures and as-dep……………………………………………………………………………18
Fig.2-3 XPS of Hf4f for HfGeOx film after annealing in N2 ambient for 30s at various temperatures and as-dep……………………………………………………………………………18
Fig.2-4 XPS of Ge3d for HfGeOx film after annealing in N2 ambient for 30s at various temperatures and as-dep……………………………………………………………………………19
Fig.2-5 XRD of HfGeOx trapping layer after anneal in N2 ambient for 30s at various temperatures………………………19
Fig.2-6 High frequency C-V (1KHz) curve of Al/HfO2/Si structure with RTA at 600℃…………………………………………20
Fig.2-7 High frequency C-V (1MHz) curve of HfO2/HfGeOx/SiO2 structure without RTA…………………………………………………20
Fig.2-8 High frequency C-V (1MHz) curve of HfO2/HfGeOx/SiO2 structure after RTA at 800℃ demonstrated the capacitor is repeatable…………………………………………………………………21
Fig.2-9 High frequency C-V (1MHz) curve of HfO2/HfGeOx/SiO2 structure after RTA at 800℃………………………………………21
Fig.2-10 High frequency C-V (1MHz) curve of HfO2/HfGeOx/SiO2 structure after RTA at 850℃…………………………………………………………………………………22
Fig.2-11 High frequency C-V (1MHz) curve of HfO2/HfGeOx/SiO2 structure after RTA at 900℃…………………………………………………………………………………22
Fig.2-12 High frequency C-V (1MHz) curve of HfO2/HfGeOx/SiO2 structure after RTA at 950℃…………………………………………………………………………………23
Fig.2-13 Programming(Vg=15V)and erasing(Vg=-15V) characteristics of HfO2/HfGeOx/SiO2 structure for RTA
800℃…………………………………………………………………………24
Fig.2-14 Programming(Vg=15V)and erasing(Vg=-15V) characteristics of HfO2/HfGeOx/SiO2 structure for RTA
850℃…………………………………………………………………………24
Fig.2-15 Programming(Vg=15V)and erasing(Vg=-15V) characteristics of HfO2/HfGeOx/SiO2 structure for RTA
900℃…………………………………………………………………………25
Fig.2-16 Programming(Vg=15V)and erasing(Vg=-15V) characteristics of HfO2/HfGeOx/SiO2 structure for RTA
950℃…………………………………………………………………………25
Fig.2-17 Room temperature charge-retention characteristics of HfO2/HfGeOx/SiO2 structure for RTA at 800℃……………26
Fig.2-18 Room temperature charge-retention characteristics of HfO2/HfGeOx/SiO2 structure for RTA at 850℃……………26
Fig.2-19 Room temperature charge-retention characteristics of HfO2/HfGeOx/SiO2 structure for RTA at 900℃……………27
Fig.2-20 Room temperature charge-retention characteristics of HfO2/HfGeOx/SiO2 structure for RTA at 950℃……………27
Fig.2-21 Charge loss rate with various temperatures at room temperature…………………………………………………………………28
Fig.2-22 (a) Pre and post-stress negative IV plot……………………………………………………………………………29
Fig.2-22 (b) Pre and post-stress positive IV plot……………………………………………………………………………29
Fig.2-23 Trapping charge and centroid for RTA at 800℃…………………………………………………………………………………30
Fig.2-24 Trapping charge and centroid for RTA at 850℃…………………………………………………………………………………30
Fig.2-25 Trapping charge and centroid for RTA at 900℃…………………………………………………………………………………31
Fig.2-26 Trapping charge and centroid for RTA at 950℃…………………………………………………………………………………31
Fig.3-1 The processes flow of HfN/HfO2/HfGeOx/HfTaOx structure……………………………………………………………………40
Fig.3-2 XRD of HfGeOx trapping layer after anneal in N2 ambient for 30s at various temperatures………………………42
Fig.3-3 XRD of HfTaOx trapping layer after anneal in N2 ambient for 30s…………………………………………………………42
Fig.3-4 High frequency C-V (1KHz) curve of Al/HfTaOx/Si structure with RTA at 700℃………………………………………43
Fig.3-5 High frequency C-V (1KHz) curve of Al/HfO2/HfTaOx/Si structure………………………………………43
Fig.3-6 High frequency C-V (1MHz) curve of HfO2/HfGeOx/HfTaOx structure without RTA…………………44
Fig.3-7 High frequency C-V (1MHz) curve of HfO2/HfGeOx/HfTaOx structure with RTA at 800℃demonstrated the capacitor is repeatable………………………………………44
Fig.3-8 High frequency C-V (1MHz) curve of HfO2/HfGeOx/HfTaOx structure with RTA at 800℃…………45
Fig.3-9 High frequency C-V (1MHz) curve of HfO2/HfGeOx/HfTaOx structure with RTA at 850℃…………45
Fig.3-10 High frequency C-V (1MHz) curve of HfO2/HfGeOx/HfTaOx structure with RTA at 900℃…………46
Fig.3-11 High frequency C-V (1MHz) curve of HfO2/HfGeOx/HfTaOx structure with RTA at 950℃…………46
Fig.3-12 Programming(Vg=11V) and erasing(Vg=-11V) characteristics of HfO2/HfGeOx/HfTaOx structure for RTA 800℃………………………………………………………………………47
Fig.3-13 Programming(Vg=11V) and erasing(Vg=-11V) characteristics of HfO2/HfGeOx/HfTaOx structure for RTA 850℃………………………………………………………………………47
Fig.3-14 Programming(Vg=11V) and erasing(Vg=-11V) characteristics of HfO2/HfGeOx/HfTaOx structure for RTA 900℃………………………………………………………………………48
Fig.3-15 Programming(Vg=11V) and erasing(Vg=-11V) characteristics of HfO2/HfGeOx/HfTaOx structure for RTA 950℃………………………………………………………………………48
Fig.3-16 Room temperature charge-retention characteristics of HfO2/HfGeOx/HfTaOx structure for RTA at 800℃………49
Fig.3-17 Room temperature charge-retention characteristics of HfO2/HfGeOx/HfTaOx structure for RTA at 850℃………49
Fig.3-18 Room temperature charge-retention characteristics of HfO2/HfGeOx/HfTaOx structure for RTA at 900℃………50
Fig.3-19 Room temperature charge-retention characteristics of HfO2/HfGeOx/HfTaOx structure for RTA at 950℃………50
Fig.3-20 Charge loss rate with various temperatures at room temperature………………………………………………………………51
Fig.4-1 Electron energy level diagram for Al/HfTaOx /p-Si structure at accumulation bias gate voltage………………56
Fig.4-2 (a)Dependence of △JT on the negative polarity gate voltage with HfTaOx gate dielectric film(EOT=45 Å)……57
Fig.4-2 (b) Dependence of △JV on the negative polarity gate voltage with HfTaOx gate dielectric film(EOT=45 Å)......……………………………………………………………………57
Fig.4-3 (a)Dependence of △JT on the negative polarity gate voltage for MOS structures with HfTaOx gate dielectric film(EOT=60 Å); two peaks are observed at VI and VII………58
Fig.4-3 (b)Dependence of △JV on the negative polarity gate voltage for MOS structures with HfTaOx gate dielectric film(EOT=60 Å)…………………………………………………………………58
Fig.4-4 (a)Dependence of △JT on the negative polarity gate voltage for MOS structures with HfTaOx gate dielectric film(EOT=75 Å)…………………………………………………………………59
Fig.4-4 (b) Dependence of △JV on the negative polarity gate voltage for MOS structures with HfTaOx gate dielectric film(EOT=75 Å)……………………………………………………………59
Fig.4-5 Dependence of second voltage peak (VII) on the EOT of HfTaOx gate dielectric stack; VII is determined from△JV curve…………………………………………………………………………60
Fig.4-6 Band diagram of HfGeOx nonvolatile memory with (a) SiO2 tunneling dielectric……………………………………………61
Fig.4-6 Band diagram of HfGeOx nonvolatile memory with (b) HfTaOx tunneling dielectric…………………………………………61
Fig.5-1 Hysteresis of SiO2 and HfTaOx tunneling dielectrics for different annealing temperature……………………………65
Fig.5-2 Programming speed of SiO2 and HfTaOx tunneling dielectrics for different annealing temperature……………65
Fig.5-3 Charge loss rate of SiO2 and HfTaOx tunneling dielectrics for different annealing temperature……………66
Chapter 1
[1]D. Kahng and S. M. Sze, Bell Syst. Tech, J., 46, 1288 (1967).
[2]M. H. White, Y. Yang, A. Purwar, and M. L. French, IEEE Int'l Nonvolatile Memory Technology Conference, 52 (1996).
[3] M.H. White, D. A. Adams, and J. Bu, IEEE circuits & devices, 16, 22 (2000)
[4]H. E. Maes, J. Witters, and G. Groeseneken, Proc. 17 European Solid State Devices Res.Conf. Bologna 1987, 157 (1988)
[5]S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, IEEE Int. Electron Devices Meeting Tech. Dig., 521 (1995)
[6]J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, IEEE Electron Device Lett., 18,278 (1997).
[7]Y. C. King, T. J. King, and C. Hu, IEEE Int. Electron Devices Meeting Tech. Dig., 115(1998).
[8]Y. N. Tan, W. K. Chim, B. J. Cho, and W. K. Choi, “Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer”, IEEE Trans. Electron Devices, vol. 51, no. 7,pp. 1143–1147, Jul. 2004.
[9]T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi,Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multibit SONOS type flash memory using a high-κ charge trapping layer,” in VLSI Symp. Tech. Dig., 2003, pp. 27–28.
[10]Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, T. H. Ng, and B. J.Cho, “High-κ HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation”, in IEDM Tech. Dig., 2004,pp. 889–892.
[11]Jong Jin Lee, Xuguang Wang, Weiping Bai, Nan Lu, and Dim-Lee Kwong “Theoretical and Experimental Investigation of Si Nanocrystal Memory Device With HfO2 High-k Tunneling Dielectric,” in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 10, OCTOBER 2003
[12]Yan Ny Tan, Wai Kin Chim, Wee Kiong Choi, Moon Sig Joo, and Byung Jin Cho, “Hafnium Aluminum Oxide as Charge Storage and Blocking-Oxide Layers in SONOS-Type Nonvolatile Memory for High-Speed Operation” in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 4, APRIL 2006
[13]Xuguang Wang and Dim-Lee Kwong, “A Novel High-k SONOS Memory Using TaN/Al2O3/Ta2O5/HfO2/Si Structure for Fast Speed and Long Retention Operation” in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 1, JANUARY 2006.

Chapter 2
[1]Yan Ny Tan; Chim, W.K.; Wee Kiong Choi; Moon Sig Joo; Byung Jin Cho, IEEE Trans. Electron Devices, vol. 53 , pp. 654-662, Jul. 2006.
[2]M. Balog, M. Schieber,M.Michman, and S. Patai,“Chemical vapor deposition and characterization of HfO films from organo-hafnium compounds,” Thin Solid Films, vol. 41, pp. 247–259, 1977.
[3]K. S. Lim and C. H. Ling,“Charge Trapping in Interpoly ONO Film”, ICSE'98 Proc., Nov. 1998

[4]Zhi Hong Liu, P. T. Lai and Yiu Chung Cheng,“Characterization of Charge Trapping and High-Field Endurance for 15-nm Thermally Nitrided Oxides”, IEEE NO. 2, pp. 344-354, 1991


Chapter 3
[1]C. H. Lee, S. H. Hur, Y. C. Shin, J. H. Choi, D. G. Park, and K. Kim,
Appl. Phys. Lett. 86, 152908 ,2005.
[2]S. Zafar, A. Callegari, V. Narayanan, and S. Guha, Appl. Phys. Lett. 81,2608 ,2002.
[3] J. J. Lee, X. Wang, W. Bai, N. Lu, J. Liu, and D. L. Kwong, Proceedings of the VLSI Technol., Symposium, 2003, p 33.
[4]D. W. Kim, T. Kim, and S. K. Banerjee, IEEE Trans. Electron Devices 50, 1823 (2003).
[5] Y.Q.Wang ,D.L.Kwong, An Yan Du and N. Balasubramanian, Appl. Phys. Lett., Vol. 84, No. 26, 28 June 2004
[6] M. H. Zhang,a_ S. J. Rhee, C. Y. Kang, C. H. Choi, M. S. Akbar, S. A. Krishnan, T. Lee,I. J. Ok, F. Zhu, H. S. Kim, and Jack C. Lee, Appl. Phys. Lett. 87, 232901 ,2005.
[7] Xiongfei Yu, Chunxiang Zhu, Mingbin Yu, and Dim-Lee Kwong, “Improvements on Surface Carrier Mobility and Electrical Stability of MOSFETs Using HfTaO Gate Dielectric” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 12, DECEMBER 2004
[8] C. Zhao a,*, T. Witters a, P. Breimer b, J. Maes c, M. Caymax a, S. De Gendt, Microelectronic Engineering 84 ,2007

Chapter 4
[1]R. Stratton, J. Phys. Chem. Solids 23, 1177 ~1962!.
[2]J. G. Simmons, Appl. Phys. Lett. 35, 2655 ~1964!.
[3] C. B. Duke, in Tunneling in Solids, edited by F. Seitz, D. Turnbull, and H.
Ehrenreich ~Academic, New York, 1969!, p. 63.
[4] S. Zafar, E. Cartier, and E. P. Gusev, Appl. Phys. Lett. 80,2749~2751
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔