臺灣博碩士論文加值系統

本論文之電路特性模擬採用安捷倫科技(Agilent) Advanced Design System (ADS)軟體，並且使用台積電(TSMC) 0.18μm CMOS製程研製『低相位雜訊壓控振盪器及超寬頻升頻混頻器』。在低相位雜訊壓控振盪器的設計中，整體特性著重於相位雜訊的表現，我們使用變壓器耦合技術去取代主動元件降低雜訊及偏壓點選擇技術做相位雜訊的最佳化，希望將來能夠應用於歐規衛星電視(DVB-S)收發機系統中。此振盪器量測結果為：相位雜訊為-115.56dBc/Hz、輸出頻率9.63GHz-10.63GHz，所計算出的FOM為-184.5dBc@1MHz，直流電壓為1V的情況下，總消耗功率為13.68mW。另外在超寬頻升頻混頻器的設計中，採用單端平衡式混頻器，希望能夠降低功率的消耗，並且設計一個超寬頻(Ultra Wide Band；UWB)馬欽德巴倫(Marchand Balun)電路做為升頻混頻器射頻訊號輸出匹配電路，希望將來能夠應用於超寬頻低功率室內無線影像傳輸發射機系統中。此混頻器模擬結果為：轉換增益為-4dB以上、輸出訊號頻率為10.1GHz至30.1GHz、基頻(BB)對射頻(RF)隔離度為-41dB、本地振盪(LO)對射頻(RF)隔離度為-30dB、三階截斷點為-5dBm、電路功率消耗為11.17mW。

This thesis presents for “A low phase noise voltage-control oscillator (VCO) and a UWB (Ultra Wide Band) up-conversion mixer” with TSMC 0.18μm 1P6M CMOS process. All circuits were designed and simulated by Advanced Design System (ADS). The low phase noise voltage control oscillator is focused on phase noise performance. We use a transformer coupling and the optimum gate biasing technology to reduce the phase noise for European DVB-S communications satellite receiver application. The measured phase noise was -115.56dBc/Hz with a turning range from 9.63 to 10.63GHz, and the calculated FOM was -184.5dBc@1MHz offset. This circuit was operated at 1V with total power dissipation of only 13.68mW. In addition for ultra wide band and low power dissipation for indoor wireless communication system, we designed an ultra wide band up-conversion mixer using single-balance structure to lower power consumption, and we designed an ultra wide band Marchand Balun circuit for up-conversion mixer output to incorporate with RF (Radio-frequency) matching network. The simulated conversion gain was upward -4dB with the RF frequency from 10.1GHz to 30.1GHz, BB (Base-band) to RF isolation of 41dB, LO (Local oscillation) to RF isolation of 30dB, IIP3 of -4.5dBm and the total power dissipation of 11.17mW.

目 錄
指導教授推薦書
口試委員審定書
圖書館授權書
致謝 iii
中文摘要 v
英文摘要 vi
章節目錄 vii
圖目錄 x
第一章 緒論
1-1 背景 1
1-2 論文電路簡介 3
第二章 射頻電路設計考量參數
2-1 射頻電路效能參數 5
2-1-1 反射係數 5
2-1-2 增益 6
2-1-3 隔離度 7
2-1-4 雜訊指數 7
2-1-5 P_1dB抑制點 10
2-1-6 輸入三階截距點(IIP3) 12
2-1-7 穩定度 14
2-1-8 品質因素 15
第三章 低相位雜訊壓控振盪器
3-1 簡介 16
3-2 工作原理 17
3-3 相位雜訊 20
3-3-1 相位雜訊由來 20
3-3-2 相位雜訊對系統的影響 21
3-4 電路設計與方法 24
3-5 量測結果 29
3-6 相關應用與發展 35
3-7 結論 37
第四章 超寬頻混頻器
4-1 簡介 38
4-2 工作原理 39
4-3 架構分析 41
4-3-1 單端平衡式混頻器 42
4-3-2 雙端平衡式混頻器 45
4-3-3 被動式混頻器 47
4-4 馬欽德巴倫(Marchand Balun) 48
4-5 模擬結果 52
4-6 相關應用與發展 61
4-7 結論 64
第五章 總結論與未來展望
5-1 總結論 65
5-2 未來展望 66
參考文獻 67

圖目錄

圖1.1 射頻前端收發機電路 3
圖1.2 設計流程圖 4
圖2.1 雙埠網路 6
圖2.2 放大器雜訊指數 8
圖2.3 兩級放大器雜訊指數 9
圖2.4 N級放大電路之雜訊指數 10
圖2.5 P_1dB抑制點 11
圖2.6 交互調變 12
圖2.7 交互調變對相鄰訊號的影響 13
圖2.8 三階截距點 13
圖2.9 Two-tone test 14
圖3.1 無線收發機系統架構圖 16
圖3.2 回授系統方塊圖 17
圖3.3 RLC諧振電路 18
圖3.4 壓控振盪器定義 19
圖3.5 VCO輸出頻譜圖 21
圖3.6 (a)理想振盪器輸出頻譜 (b)實際振盪器輸出頻譜 22
圖3.7 理想振盪器降頻示意圖 23
圖3.8 實際振盪器降頻示意圖 24
圖3.9 單端輸出考畢子振盪器 25
圖3.10 差動式考畢子振盪器 26
圖3.11 壓控振盪器電路架構圖 27
圖3.12 偏壓點選擇處 28
圖3.13 (a)一般設計之壓控振盪器輸出頻譜 29
圖3.13 (b)偏壓點選擇技術壓控振盪器輸出頻譜 29
圖3.14 相位雜訊模擬與量測結果比較 31
圖3.15 可調頻寬模擬與量測結果比較 31
圖3.16 輸出功率對控制電壓模擬與量測結果比較 32
圖3.17 相位雜訊對控制電壓模擬與量測結果比較 32
圖3.18 壓控振盪器輸出波形表現圖 32
圖3.19 (a)相位雜訊儀器照相圖 (b)輸出頻譜儀器照相圖 33
圖3.20 FOM於控制電壓內的表現(1MHz offset) 33
圖3.21 不同VBuff電壓下相位雜訊對主諧波與三階諧波差值關係 34
圖3.22 (a)晶片佈局圖 (b)晶片量測圖 34
圖3.23 DVB-S系統示意圖 36
圖3.24 LNB架構圖 36
圖4.1 混頻器示意圖 39
圖4.2 混頻器架構(a)單端平衡式 (b)雙端平衡式 (c)被動開關式 42
圖4.3 單端平衡式混頻器等效電路 43
圖4.4 單端平衡混頻器操作原理 43
圖4.5 混頻器輸出端頻譜 44
圖4.6 雙端平衡式混頻器電路架構 46
圖4.7 被動式混頻器架構 48
圖4.8 Marchand Balun之基本架構 50
圖4.9 Marchand Balun電路配置圖 51
圖4.10 新型Marchand Balun架構圖 51
圖4.11 10GHz~30GHz超寬頻升頻混頻器電路架構圖 54
圖4.12 Marchand Balun 10GHz~30GHz返迴損耗表現 55
圖4.13 Marchand Balun之輸出相位差 56
圖4.14 Marchand Balun 10GHz~30GHz插入損耗表現 56
圖4.15 混頻器轉換增益圖 56
圖4.16 混頻器隔離度表現(BB to RF) 57
圖4.17 混頻器隔離度表現(LO to RF) 57
圖4.18 混頻器IIP3表現 57
圖4.19 轉換增益對基頻訊號線性度表現 58
圖4.20 轉換增益對本地振盪訊號線性度表現 58
圖4.21 混頻器輸出頻譜圖 59
圖4.22 晶片佈局圖 61
圖4.23 10GHz~30GHz超寬頻無線發射機系統架構圖 62

表目錄
表3.1 壓控振盪器與參考文獻比較表 35
表4.1 混頻器Pre-sim與Pro-sim比較表 59
表4.2 超寬頻混頻器與參考文獻比較表 60
表4.3 超寬頻混頻器預計規格列表 60
表4.4 超寬頻發射機預計規格列表 62

參考文獻
[1] C. S. Harsany, Principles of Microwave Technology. New Jersey: Prentice-Hall, 1997.
[2]G. Gonnalez, Microwave Transistor Amplifier Analysis and Design 2nd edition. New Jersey: Prentice-Hall, 1997.
[3]袁帝文, 王岳華, 謝孟翰, 王弘毅, 《高頻通訊電路設計》.高立圖書, 2000.
[4]B. Razavi, RF Microelectronics. New Tersey: Prentice-Hall, 1998.
[5]W. S. Kim, X. Li, and M. Ismail, “2.4GHz CMOS LNA using an interstage matching inductor,” in Proc.42nd Midwest Symp. Circuits Sys, Vol.2, pp. 1040-1043, Aug. 1999.
[6]D. M. W. Leenaerts, J. van der Tang and Cicero S. Vaucher, “Circuit Design for RF transceivers,” Boston:Kluwer, 2001.
[7]H. Kim, S. Ryu, Y. Chung, J. Choi, and B. Kim, “A Low Phase Noise CMOS VCO With Harmonic Tuned LC Tank,” IEEE Transactions On Microwave Theory And Techniques, vol, 54, No.7, pp. 2917 – 2924, July 2006.
[8]T. K. Tommy, N. El-Gama1 Mourad “A high figure of merit and area-efficient low-voltage (0.7–1 V) 12 GHz CMOS VCO,” In: IEEE Radio Frequency Integrated Circuits Symposium, pp. 89 – 92, 2003.
[9]N. J. Oh, S. G. Lee, “11-GHz CMOS differential VCO with back-gate transformer feedback,” IEEE Microw Wireless Compon Lett 15(11), pp. 733 – 735, 2005.
[10]H. Yiping, E. L. Lawrence, D. Lie,” A low-voltage 12GHz VCO in 0.13um CMOS for OFDM Application”, SiRF. pp. 379-382, 2006.
[11]G. Girlando, S. A. Smerzi, T. Copani, and G. Palmisano, “A Monolithic 12-GHz Heterodyne Receiver for DVB-S Applications in Silicon Bipolar Technology”, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO.3 pp. 952 – 959. MARCH 2005.
[12]J. C. Chiu, C. M. Lin, and Y. H. Wang, “A 3-dB Quadrature Coupler Suitable for PCB Circuit Design,” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 9, pp. 3521-3525 EPTEMBER 2006.
[13]S. M. Perlow, “The Interdigitated Three-Strip Coupler” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. MTT-32, NO.10, pp. 1418-1422, OCTOBER 1984.
[14]I. C. H. Lai, “An Integrated 20-26 GHz CMOS Up-Conversion Mixer with Low Power Consumption,” pp. 400 – 403 19-21 Sept. 2006.
[15]A. Verma, “A Low-Power Up-Conversion CMOS Mixer for 22–29GHz Ultra-Wideband Applications”, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 8, pp. 3295-3300 AUGUST 2006.
[16]P. C. Huang, R. C. Liu, J. H. Tsai, H. Y. Chang, H. Wang, J. Yeh, C. Y. Lee, and J. Chern, “A Compact 35-65 GHz Up-Conversion Mixer with Integrated Broadband Transformers in 0.18-um SiGe BiCMOS Technology” IEEE RFIC Symposium, pp. 224-228, 11-13 June 2006.
[17]賴永齡副教授、黃建彰副教授、邱煥凱副教授,《微波積體電路設計》桃園,中央大學,2006.
[18]D. B. Leson, “A simple model of feedback oscillator noise spectrum,” Proc. of the IEEE, vol. 54, no. 2, pp. 329–330, Feb. 1966.
[19]A. Hajimiri, Lee TH. “A general theory of phase-noise in electrical oscillators,” IEEE, J Solid-State Circuits, pp. 179-194, Feb. 1998.
[20] E. van der Heijden, A. Farrugia, R. Breunisse, C.S. Vaucher and R. Pijper, “Colpitts VCOs for Low Phase-Noise and Low Power Applications With Transformer-Coupled Tank,” IEEE RFIC Symposium, pp. 653-656, 17 June. 2008.
[21]C. H. Chang, C. Y. Yang, “A Low-Voltage High-frequency CMOS LC-VCO Using a Transformer Feedback,” IEEE RFIC, pp. 545-548, June. 2008.