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研究生:陳俊生
研究生(外文):Jun Son Chen
論文名稱:五氧化二鉭閘極絕緣層與薄膜電晶體之研究
論文名稱(外文):The Study of Ta2O5 Dielectric in Thin Film Transistors
指導教授:高泉豪
指導教授(外文):C. H. Kao
學位類別:碩士
校院名稱:長庚大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:96
論文頁數:84
中文關鍵詞:高介電材料複晶矽高介電絕緣層電容氮氫電漿處理
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在本論文中,係應用高介電材料五氧化二鉭做為低溫多晶矽薄膜電晶體之介電層。結合使用後段電漿處理技術來修補五氧化二鉭和複晶矽之間的晶界缺陷,因而提昇改善低溫多晶矽薄膜電晶體之特性。
首先,我們使用五氧化二鉭與氮化鈦來製作成電容沉積於複晶矽薄膜上,並加上後段氫電漿(H2)之處裡,可使所製作的複晶矽高介電絕緣層電容有較大的崩潰電壓和較低漏電流。主要是經過後段氫電漿處理後,氫離子可修補高介電絕緣層內的缺陷以及五氧化二鉭與複晶矽界面間的缺陷能態,同時並形成較好的矽氫鍵結來改善電容的特性。
接著,我們也使用氮氫電漿(NH3)來做修補處理,應用在所製作的複晶矽高介電絕緣層電容,其電性上亦有所改善。使用氮氫電漿處理後,可以抑制介面層成長,得到較薄的EOT之外,也可以形成較好的矽氮鍵結來改善電容的特性,在漏電流、崩潰電場、崩潰電荷上皆可得到明顯的改善。
最後,我們實際的使用高介電材料五氧化二鉭做為低溫多晶矽薄膜電晶體之介電層,同時並結合氮氫電漿來做缺陷的修補處理,可以看到低溫多晶矽薄膜電晶體元件的電性上皆有改善。包含了截止區的漏電流、導通區的驅動電流、崩潰電壓以及多晶矽邊界的缺陷密度等。此乃由於氮氫離子填補了多晶矽通道以及邊界間的缺陷密度,並且在多晶矽和高介電材料絕緣層的界面形成比較強的鍵結,以取代原本較弱的鍵結來改善元件的電性。
In this thesis, we apply a new high-K material Ta2O5 as the dielectric layer in low temperature Poly-Si TFT. The post plasma treatment was combined to passivate the interface states of grain boundary between the Ta2O5 and polysilicon layer. Furthermore, the characteristics of the LTPS TFT’s transistors were improved.
At first, Ta2O5 and TaN materials were used to fabricate the capacitors deposited on the polysilicon layer. Those high-K polyoxide capacitors after the hydrogen post plasma treatment can obtain larger breakdown fields and lower leakage currents. The is due to the released hydrogen ion can passivate the traps and defects existed in high-K material and the interface states in the grain boundary to form more strong Si-H bondings for the quality improvements.
On the other hand, another post NH3 plasma treatment was used to apply in the high-K polyoxide capacitors for improvements. Using the NH3 post plasma treatment, the growth of interfacial layer can be suppressed to get thinner effective oxide thickness (EOT); and the formation of strong Si-N bondings can improve the electrical characteristics such as lower leakage currents, higher breakdown voltages and larger charg-to-breakdown.
Finally, we also demonstrated that the Ta2O5 as the gate insulator combined with NH3 post plasma treatment can improve the performances of the poly-Si TFT transistors, which including off-state leakage currents, on-state driving currents, threshold voltages and grain-boundary trap-state densities. These improvements are also attributed to be due to the hydrogen and nitrogen ions can passivate the trap-states existed in the Ta2O5/polysilicon interface and grain-boundary effectively and form more strong bondings for performance improvements.
Contents
Acknowledgment i
Chinese Abstract ii
English Abstract iv
Contents vi
Figures Captions and Tables viii
Chapter 1 Introduction………………………………………………………1
1.1 Background………………………………………………………1
1.1.1 High-k Gate Dielectric………………………………3
1.2 Motivation………………………………………………………4
1.3 Thesis Organization…………………………………………5
Reference……………………………………………………7
Chapter 2 Characteristics of Ta2O5 Polyoxide Capacitors with H2 plasma post-treatment…………………………………………11
2.1 Introduction…………………………………………………11
2.2 High-K Material Etching…………………………………11
2.2.1 High-K Etching Introduction…………………11
2.2.2 High-K Etching Experiments…...........12
2.2.3 Etching Result……………………………………13
2.3 Ta2O5 polyoxide capacitors with H2 plasma
post-treatment………………………………………………15
2.3.1 Experiment …………………………………………15
2.3.2 Results an d Discussion…………………………16
2.3.3 Summary………………………………………………18
Reference……………………………………………………19
Chapter 3 Characteristics of Ta2O5 Polyoxide capacitors with NH3 plasma post-treatment………………………………………29
3.1 Introduction…………………………………………………29
3.2 Experiment……………………………………………………30
3.3 Results and Discussion…………………………………31
3.4 Summary………………………………………………………32
Reference…………………………………………………………33
Chapter 4 The Effects of Low-Temperature Poly-Si TFTs with High-k Ta2O5 Gate dielectric by NH3 Plasma Post-treatment.43
4.1 Introduction…………………………………………………43
4.2Experiment………………………………………………………44
4.3 Method of device parameter extracti………………45
4.3.1 Introduction……………………………………………45
4.3.2 Determination of field effect mobility(μFE).. 45
4.3.3 Determination of threshold voltage………………47
4.3.4 Determination of subthreshold swing………………48
4.3.5 Determination of On/Off current ratio……………49
4.3.6 Extraction of grain boundary trap state…………50
4.4 Results and Discussion……………………………………52
4.5 Summary……………………………………………………………54
Reference………………………………………………………………55
Chapter 5 Conclusions and Future Works……………………………66
5.1 Conclusion………………………………………………………66
5.2 Future works……………………………………………………66
Publications List…………………………………………………68

Figures Captions and Tables
Chapter 1
Table. 1-1 This sheet is a demonstration aboutthe comparisions of physical characteristics of High-k.
Chapter 2
Table. 2-1 Different etching solution to High-k etch ratemeter
Table. 2-2 The detail etching process of TiN/Ta2O5 films.
Fig. 2-1 Schematic polyoxide capacitors cross-section detailed process flow
Fig. 2-2 The high frequency C-V characteristics of aluminum/polyoxide/n+polysilicon for control sample with a CET 97.9Å
Fig. 2-3 The high frequency C-V characteristics of aluminum/polyoxide/n+polysilicon for H2 post-treatment 30 min sample with a CET 95.5Å
Fig. 2-4 The high frequency C-V characteristics of aluminum/polyoxide/n+polysilicon for H2 post-treatment 60 min sample with a CET 91.169Å
Fig. 2-5 The J-V characteristics of the control, post-H2 30 min and 60min treatment on gate dielectric/n+polysilicon films for the top gate applied with a negative bias
Fig. 2-6 The J-V characteristics of the control, post-H2 30 min and 60 min treatment on gate
dielectric/n+polysilicon films for the top gate applied with a positive bias
Fig. 2-7 The curves of gate voltage shifts (△Vg) versus stress time of the control, post-H2 30 min and 60 min treatment on gate dielectric/n+polysilicon films for the top gate applied with a negative gate constant current (under -0.5 μA/cm2) stess
Fig. 2-8 The curves of gate voltage shifts (△Vg) versus stress time of the control, post-H2 30 min and 60 min treatment on n+polysilicon films for the top gate applied with a positive gate constant current(under -0.5 μA/cm2) stress
Fig. 2-9 The Weibull distribution Qbd plots for the control, post-H2 30 min and 60 min treatment on gate dielectric/n+polysilicon films for the top gate applied with a negative bias
Fig. 2-10 The Weibull distribution Qbd plots for the control, post-H2 30 min and 60 min treatment on gate dielectric/n+polysilicon films for the top gate applied with a positive bias
Fig. 2-11 SIMS profile analysis of control and post-H2 60 min
Fig. 2-12 AFM images of n+polysilicon surface of control sample with roughness root mean square (rms) of 3.9882nm
Fig. 2-13 AFM images of n+polysilicon surface of post-H2 30 min sample with roughness root mean square (rms) of 4.128 nm
Chapter 3
Fig. 3-1 Schematic polyoxide capacitors cross-section detailed process flow
Fig. 3-2 The high frequency C-V characteristics of aluminum/polyoxide/n+polysilicon for control sample with a CET 97.9Å
Fig. 3-3 The high frequency C-V characteristics of aluminum/polyoxide/n+polysilicon for post-NH3 30 min sample with a CET 89.23Å
Fig. 3-4 The high frequency C-V characteristics of aluminum/polyoxide/n+polysilicon for post-NH3 60 min sample with a CET 87.19Å
Fig. 3-5 The J-V characteristics of the control, post-NH3 30 min and 60 min teatment on gate dielectric/n+polysilicon films for the top gate applied with a negative bias
Fig. 3-6 The J-E characteristics of the control, post-NH3 30 min and 60 min treatment on gate dielectric/n+polysilicon films for the top gate applied with a positive bias
Fig. 3-7 The curves of gate voltage shifts (△Vg) versus stress time of thecontrol, post-NH3 30 min and 60 min treatment on gate dielectric /n+polysilicon films for the top gate applied with a negative gate constant current (under -0.5 μA/cm2) stress
Fig. 3-8 The curves of gate voltage shifts (△Vg) versus stress time of the control, post-NH3 30 min and 60 min treatment on gate dielectric /n+polysilicon films for the top gate applied with a positive gate constant current (under 0.5 μA/cm2) stress
Fig. 3-9 The Weibull distribution Qbd plots for the control, post-NH3 30 min and 60 min treatment on gate dielectric/n+polysilicon films for the top gate applied with a negative bias
Fig. 3-10 SIMS profile analysis of s post-NH3 30 min and 60 min
Fig. 3-11 AFM images of n+polysilicon surface of control sample with roughness root mean square (rms) of 3.882 nm
Fig. 3-12 AFM images of n+polysilicon surface of control sample with roughness root mean square (rms) of 4.115 nm
Fig. 3-13 AFM images of n+polysilicon surface of control sample with roughness root mean square (rms) of 4.329 nm
n+polysilicon for post-NH3 60 min sample with a CET 87.19Å
Fig. 3-5 The J-V characteristics of the control, post-NH3 30 min and 60 min teatment on gate dielectric/n+polysilicon films for the top gate applied with a negative bias
Fig. 3-6 The J-E characteristics of the control, post-NH3 30 min and 60 min treatment on gate dielectric/n+polysilicon films for the top gateapplied with a positive bias
Fig. 3-7 The curves of gate voltage shifts (△Vg) versus stress time of thecontrol, post-NH3 30 min and 60 min treatment on gate dielectric/n+polysilicon films for the top gate applied with a negative gate constant current (under -0.5 μA/cm2) stress
Fig. 3-8 The curves of gate voltage shifts (△Vg) versus stress time of the control, post-NH3 30 min and 60 min treatment on gate dielectric /n+polysilicon films for the top gate applied with a positive gate constant current (under 0.5 μA/cm2) stress
Fig. 3-9 The Weibull distribution Qbd plots for the control, post-NH3 30 min and 60 min treatment on gate dielectric/n+polysilicon films for the top gate applied with a negative bias
Fig. 3-10 SIMS profile analysis of s post-NH3 30 min and 60 min
Fig.3-11 AFM images of n+polysilicon surface of control sample with roughness root mean square (rms) of 3.882 nm
Fig.3-12 AFM images of n+polysilicon surface of control sample with roughness root mean square (rms) of 4.115 nm
Fig. 3-13 AFM images of n+polysilicon surface of control sample with roughness root mean square (rms) of 4.329 nm
Fig.3-14 N 1s XPS spectra for polysilicon surface with without NH3 plasma.
Fig.3-15 (a) Ta 4d5 (b) O 1s spectra for polysilicon surface with without NH3 plasma.
Chapter 4
Fig. 4-1 The detailed process flow of low temperature TFTs is listed as following
Fig. 4-2 The C-V characteristics of TiN metal gate/Ta2O5/polysilicon capacitors for control, post-NH3 30 min and 60 min treatment
Fig. 4-3 Transfer characteristics of the control, post-NH3 30 min and 60 min treatment for LTPS TFTs
Fig. 4-4 Output characteristics of the control, post-NH3 30 min and 60 min treatment for LTPS TFTs
Fig. 4-5 The grain-boundary trap-states extraction of the control, post-NH3 30 min and 60 min treatment for LTPS TFTs
Table. 4-1 Device parameters of LTPS TFTs for control, post-NH3 30min and 60min treatment at VDS=0.1V
chapter 1
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chapter 2
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chapter3
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chapter4
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