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研究生:歐李啟祥
研究生(外文):Chi-Shuang Oulee
論文名稱:全數位時脈資料回復電路之設計與應用
論文名稱(外文):Design and Application of All-Digital Clock and Data Recovery Circuit
指導教授:李建德李建德引用關係
指導教授(外文):J. D. Lee
學位類別:碩士
校院名稱:長庚大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
論文頁數:91
中文關鍵詞:時脈資料回復電路
外文關鍵詞:Clock and Data Recovery Circuit
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隨著CMOS製程的進步,有越來越多的數位電路整合到一顆IC之中,因此現今的商品可以提供有需多方便介面的功能給使用者,讓使用者可以輕易的槍數位化的多媒體訊息傳送到個人電腦或是個人數位助理上,並經由網際網路與朋友分享。因此,在給手持式裝置所使用的有線傳輸介面,以及光纖網路的需求逐漸增加。隨著有線通訊系統資料速率的提升,電路操作的時間安全範圍漸漸變短,而時脈的相位誤差和抖動將使得操作這些數位電路變的困難,所以在時脈資料回復的電路設計上也更困難。

鎖相迴路廣泛地應用在時脈同步電路、頻率合成器以及時脈及資料回復電路,由於它可以達成時脈同步的特性,在通訊系統中更是不可或缺的。由於傳統的資料回復電路使用類比的方式來實現,因此有較好的時脈抖動表現(Jitter Performance),但是需要較長的時間來達成鎖定,同時需要較大的迴路電容,在系統整合上較為困難。由於類比實現的方式對雜訊及製程電壓溫度變異(PVT Variations)較為敏感,更換製程之後往往需要重新設計,無法隨著製程的發展而進步。

本論文中介紹了使用二元頻率追蹤與壓制抖動電路的不需要參考時脈的全數位式資料回復電路。此電路基本上是將一個典型的資料時脈回復電路裡的類比迴路濾波器與壓控震盪器換成數位的迴路濾波器與數位控制震盪器。另外也分析以及預測了數位資料時脈回復電路的非線性行為。特別是推導以及改進了長的資料的影響以及數位濾波的取樣率的影響。
With the progress of the CMOS technologies, more and more digital circuits are integrated in a monolithic IC. Thus the commercial products can provide many useful functions with friendly user interfaces for the customers. The digitized multi-media information can be transferred into personal computers or personal digital assistant and shared with friends via the internet. Thus the demands of the high-speed wired-line interfaces for the handheld devices and the optical communication network for the internet grow gradually. As the increase of the baud rate for the wired-line communications, the timing margin for the wired-line transceivers is shrinking. Hence the challenge for the clock /data recovery circuits also advances.

Phase-locked loops are widely used in clock de-skew buffer, frequency synthesizer and clock/data recovery. It is indispensable in communications because of the character of the synchronization. The traditional clock and data recovery circuits keeps good jitter performance due to the analog implemented, but the long lock-time and the demand of large loop capacitance cause the difficulty of the system integration. Because of the sensitivity of the analog circuit, as often as not the system must redesigned after the change of the process, and can not progress with the development of the process.

This paper describes an all-digital clock and data recovery (ADCDR) system with a fast frequency acquisition using binary search algorithm and a modified bang-bang type phase detector. The ADCDR is based on replacing the analog loop filter and voltage-controlled oscillators (VCOs) in a typical reference-free CDR with digital loop filter and digital-controlled oscillator. Additionally, the nonlinear dynamics of ADCDR is analyzed and predicted. In particular, the effect of long run-length data and sampling rate of digital implemented loop filter are derived and improved.
Contents


Chapter 1 Introduction……………………………………………….1

Chapter 2 The Basic of Clock/Data Recovery Circuit……………...….5

2.1 CDR Architectures ……...………………………………………………………5
2.1.1 Reference-less CDR Circuit…...………………………………………7
2.1.2 PLL Based CDR Circuit……………………………………………….8
2.2 Building Blocks………...….…………………………………………………10
2.2.1 Frequency Detector……….…...……………………………………10
2.2.2 Linear Phase Detector………………………………...……………14
2.2.3 Bang-Bang Phase Detector…………………………………………...20
2.3 Time-Domain Model………………………………………….......……………22

Chapter 3 Reference All-Digital CDR Circuit………...………………31
3.1 Architecture Description……………………….………………………………31
3.2 Circuit Description…….…….…….…………………………………………...34
3.2.1 Frequency detector…………………………..…………………….....34
3.2.2 Successive Approximation Register Controller………………...…....37
3.2.3 Lock Detector………………………………………………………...40
3.2.4 Digital Loop Filter…………………………………………………....41
3.2.5 DCO…………………………………………………………………43
3.3 Simulation results…….…….…….…………………………………………...45

Chapter 4 All-Digital CDR Circuit with Fast Lock & Jitter Suppressing Techniques………………………………………………………………49
4.1 Circuit Description……………………….…….………………………………55
4.1.1 Proposed Frequency Detector……………..…………………………55
4.1.2 Proposed phase detector…………………………………………….62
4.1.3 DCO…………………………………………... ………..……………64
4.2 Simulation Results……………………….…….………………………………65

Chapter 5 Conclusions ………………………………………….69

Bibliography…...……………………...………..………………….....…79




























List of Tables



Table 3.1 The probability of the frequency estimation….…………………………....35
Table 3.2 The truth table for the combination logic circuits…………………….....35
Table 4.1 The truth table for the combination logic circuits…………………….....60
Table 4.2 The truth table for the combination logic circuits…………………….....61
Table 4.3 Performance Summary……………………………………………….........67


















































List of Figures



Fig. 1.1 the point-to-point wire line communications system………………………....2
Fig. 2.1 a primary operation of a CDR circuit…………………………………………5
Fig. 2.2 optimum sampling of noisy data……………………………………………...6
Fig. 2.3 the typical topology of the reference-less CDR architecture…………………7
Fig. 2.4 the typical topology of the PLL-based CDR…………….……………………9
Fig. 2.5 The basic quadric-correlator structure……………………………………….11
Fig. 2.6 The balanced quadric-correlator structure………………………………..…13
Fig. 2.7 The digital quadric-correlator structure…………………………………......14
Fig. 2.8 The state transition of the Quadri-correlatior and the combinational logic…15
Fig. 2.9 The Hogge phase detector…………………………….…………………......17
Fig. 2.10 The corresponding timing diagrams for the leading, locked and lagging clocks…………………………………………………………………………17
Fig. 2.11 linear sample-and-hold phase detector………….………………………….19
Fig. 2.12 proportional phase tracking detection method…………………………......19
Fig. 2.13(a) A simple Bang-Bang phase detector and (b) the timing diagram…….....20
Fig. 2.14(a) The Alexander phase detector and (b) the sampling point of the Alexander phase detector…………………………………………………………...21
Fig. 2.15 (a) the typical model of the reference-free digital CDR which operates in phase tracking process and (b) the timing diagram……..........................23
Fig. 2.16 Pull-in trajectory ………………………………………………………..…26
Fig. 2.17 the phase accumulation trajectory …………………………………………28
Fig. 2.18 (a) the timing diagram of the conventional PD and (b) the phase relationship between the data and the clock………………………………………….29
Fig. 3.1 The proposed reference-less all-digital CDR……………………………......33
Fig. 3.2 The timing diagram for the operation of the proposed all-digital CDR……..33
Fig. 3.3 (a) the proposed frequency detector with combinational logic and (b) the six states of the proposed frequency detector…………………....................34
Fig. 3.4 The probability enhancement circuit………………………………………...36
Fig. 3.5 schematic of 8-bit SAR controller……………………………………….....38
Fig. 3.6 internal structure of kth flip-flop………………………....…………………..38
Fig. 3.7 the generation of the signals COMP and SAR_CLK …………………......39
Fig. 3.8 (a) schematic of the decoder (b) schematic of the MUX…………………....39
Fig. 3.9 schematic of lock detector schematic……………………………….....…….41
Fig. 3.10 the configuration of the digital loop filter………………………………….42
Fig. 3.11 the presettable counter unit………………………………………………...42
Fig. 3.12 the structures of the SAR controller, the digital loop filter and the DCO….43
Fig. 3.13 the delay cell of three-stage ring digital-controlled oscillator……………..43
Fig. 3.14 the structure of the three-stage ring oscillator and the corresponding time diagram………………………………………………………………….44
Fig. 3.15 chip layout……………………………………………………………….....46
Fig. 3.16 DCO transfer curve…………………………………………………….......46
Fig. 3.17(a) data eye (b) the recovered clock…………………………………….......47
Fig. 3.18(a) the simulation timing diagram of the proposed all-digital CDR………..47
Fig. 3.18(b) the transient response of the DCO control digit in a function of time.…48
Fig. 4.1 (a) the timing diagram of the proposed PD and (b) the phase relationship between the data and the clock……………………………………….....50
Fig. 4.2 The proposed all-digital CDR with the proposed frequency detector and the jitter suppressing circuit………..………………………………………52
Fig. 4.3 The timing diagram of the proposed all-digital CDR…………………….....53
Fig. 4.4 The proposed configuration of the digital loop filter………………………..54
Fig. 4.5 The time-domain model of the proposed reference-less all-digital CDR which operates in phase tracking mode …………………………………….....54
Fig. 4.6 (a) the proposed frequency detector with combinational logic and (b) the six states of the proposed frequency detector........…………………………56
Fig. 4.7 (a) the state transition from state I to state VI when the clock is slower than the data and (b) the state transition from state I to state II when the clock is faster than the data ………………………………………….....57
Fig. 4.8 The timing diagram of the state transition from state I to state VI while the data is random.…………………………………………...…………......58
Fig. 4.9 (a) the control pulse generator, (b) control logic circuit and (c) the conventional phase detector………………………….……………........63
Fig. 4.10 (a) the timing diagram of the control pulse generator and (b) the timing diagram of the phase tracking behavior…………………....……………64
Fig. 4.11 the delay cell of three-stage ring digital-controlled oscillator.......................65
Fig. 4.12 chip layout………………..…………………………………………….......66
Fig. 4.13(a) the simulated eye diagram of the recovered data (b) the recovered clock.........................................................................................................66
Fig. 4.14(a) 85ps@PRBS 211-1 (conventional PD) (b) 62ps@PRBS 211-1 (proposed PD)………………………...…………………………………………….66
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