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研究生:鄭期成
研究生(外文):Eric Cheng
論文名稱:以軟體控制的三角積分調變解調變系統
論文名稱(外文):A Software-Controlled Sigma-Delta Codec System
指導教授:許能傑許能傑引用關係毛大喜
指導教授(外文):Neng-jye Hsu
學位類別:碩士
校院名稱:中華技術學院
系所名稱:電子工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:96
語文別:英文
論文頁數:49
中文關鍵詞: 非線性 三角 方法 簡稱 缺點
外文關鍵詞:sigma-deltaDACdesignsystemdata
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雖然Multi-bit Sigma-Delta AD/DA具備品質穩定、架構簡單、成本低廉等優點,但是多位元類比電路帶來的非線性缺點還是必須使用特殊技巧來克服。動態元件匹配Dynamic Element Matching (以下簡稱DEM) 便是其中常用的方法,舉例說明使用DEM做Multi-bit Sigma-Delta DAC的架構
ABSTRACT

This research focuses on developing a software-controlled sigma-delta () data conversion system based on existing computing systems such as personal computers. The proposed codec system features with a hardware-implemented, re-configurable A/D modulator and other software-programmed D/A modulator and digital filters to provide various audio signal processing capability for different audio applications, improving the restriction on the conventional codec systems which may need miscellaneous circuit density, sophisticated circuit design, and high production cost for implementation.
To implement a re-configurable sigma-delta modulator for the proposed system, a cascaded architecture along with DAC nonlinearity compensation techniques has been introduced. Simulation results show that multibit cascaded sigma-delta modulators combined with data-weighted averaging for the DAC elements can effectively reduce the DAC error and alleviate the SNR loss. Therefore, a high resolution A/D modulator can be implemented according to application needs.
Based on the proposed idea, a software-controlled  codec system is built. This system is comprised of re-configurable A/D modulator and symmetric digital filters to simplify the software programming. In addition, the D/A modulator is designed to be capable of dealing with high-resolution audio signals. The feasibility of the proposed system is approved by the behavioral simulation results.
TABLE OF CONTENTS

ACKNOWLEDGMENTS i
ABSTRACT ii
LIST OF TABLES v
LIST OF FIGURES vi
CHAPTER
I. INTRODUCTION 1
II. FUNDAMENTALS OF DATA CONVERSION 4
2.1 Types of Data Converters 4
2.1.1 Nyquist-Rate Data Converters 5
2.1.2 Oversampled Sigma-Delta Data Converter 7
2.2 Properties of Quantization 8
2.3 Performance Metrics 11
III. SIGMA-DELTA MODULATION AND ITS IMPLEMENTATION 13
3.1 Principles of Sigma-Delta Modulation 13
3.1.1 Linearized Model 13
3.1.2 Stability and Overload 16
3.2 Architectures of Sigma-Delta Modulators 17
3.2.1 Single-bit High-Order Topology 17
3.2.2 Cascaded Topology 18
3.2.3 Multibit  Modulators 20
3.2.4 Comparisons of Modulator Architecture 21
IV. A SOFTWARE-CONTROLLED SIGMA-DELTA CODEC SYSTEM 23
4.1 The Conventional Codec System 23
4.2 The Proposed System 28
V. A RECONFIGURABLE SIGMA-DELTA ADMODULATOR FOR THE
SOFTWARE CONTROLLED CODEC 32
5.1 A Reconfigurable Cascaded  Modulator 32
5.1.1 Analog Nonlinearities 33
5.1.2 Solutions for the Nonlinearities 37
5.1.3 A Cascaded (1-1-1)  Modulator 37
5.1.4 Dynamic Element Matching Techniques 40
5.2 Design of the Proposed System 44
VI. CONCLUSIONS 48
REFERENCES 49
REFERENCES

[1]S. Rabii and B. Wooley, “A 1.8V digital-audio sigma-delta modulator in 0.8m CMOS,” IEEE J. Solid-State Circuits, vol. SC-32, no. 6, pp. 783-796, Jun. 1997.

[2]E. Fogleman et al., “A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB Peak SFDR,” IEEE J. Solid-State Circuits, vol. SC-35, no. 3, pp. 297-307, Mar. 2000.

[3]Y. Greets, M. Marques, M. Steyaert, and W. Sansen, “A 3.3-V, 15-bit delta-sigmal ADC with a signal bandwidth of 1.1 MHz for ADSL applications,” IEEE J. Solid-State Circuits, vol. SC-34, no. 7, pp. 927-936, Jul. 1999.

[4]J. Morizio et al., “14-b 2.2-MS/s sigma-delta ADC,” IEEE J. Solid-State Circuits, vol. SC-35, no. 6, pp. 968-976, Jul. 2000.

[5]K. Falakshahi, C. Yang, and B. Wooley, “A 14-bit 10-Msamples/s D/A converter using multibit  modulation,” IEEE J. Solid-State Circuits, vol. SC-34, no. 5, pp. 607-615, May 1998.

[6]F. Mederio, B. Perez-Verdu, and A. Rodriguez-Vazquez, “A 13-b 2.2-MS/s, 55-mW, Multi-bit cascaded sigma-delta modulator in CMOS 0.7-μm signal-poly technology,” IEEE J. Solid-State Circuits, vol. SC-34, no. 6, pp. 748-760, Jun. 1999.

[7]L. Breems, E. van der Zwan, and J. Huijsing, “A 1.8mW CMOS  modulator with integrated mixer for A/D conversion of IF signals,” IEEE J. Solid-State Circuits, vol. SC-35, no. 4, pp. 468-475, Apr. 2000.

[8]J. Franca and Y. Tsivids, Design of Analog-to-Digital VLSI Circuits for Telecommunications and Signal Processing, Chapters 9 & 12, Prentice Hall Inc., Englewood Cliffs, NJ, 1994.

[9]B. Razavi, Principles of Data Conversion System Design, IEEE Press, New York, NY, 1995.

[10]R. Geiger, P. Allen, and N. Strader, VLSI Design Techniques for Analog and Digital Circuits, Chapter 8. McGraw-Hill Publishing Inc., New York, NY, 1990.

[11]J. Candy and G. Temes, Oversampling Delta-Sigma Data Converters: Theory, Design, and Simulation, IEEE Press, New York, NY, 1992.

[12]S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation, IEEE Press, New York, NY, 1997.

[13]M. Rebeschini, “The design of cascaded  ADCs,”: Delta-Sigma Data Converters: Theory, Design, and Simulation, IEEE Press, New York, NY, 1997.

[14]R. Carley, R. Schreier, and G. Temes, “Delta-sigma ADCs with multi-bit internal converters,”: Delta-Sigma Data Converters: Theory, Design, and Simulation, IEEE Press, New York, NY, 1997.

[15]R. Adams and R. Schreier, “Stability theory for  modulators,”: Delta-Sigma Data Converters: Theory, Design, and Simulation, IEEE Press, New York, NY, 1997.

[16]R. Plassche, Integrated Analog-to-Digital and Digitla-to-Analog Converter, Kluwer Academic Publisher, Norewll, MA, 1994.

[17]I. Opris, B. Wong, and S. Chin, “A pipeline A/D converter architecture with low DNL,” IEEE J. Solid-State Circuits, vol. SC-35, no. 2, pp. 281-285, Feb. 2000.

[18]S. Rabii and B. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, Chapter 3, Kluwer Academic Publishers Inc., Norwell, MA, 1999.

[19]J. Candy and O. Benjamin, “The structure of quantization noise from sigma-delta modulation,” IEEE Trans. Commun., Vol. COM-29, pp. 1316-1323, Sep. 1981.

[20]S. Lipshitz, R. Wannamaker, and J. Vanderkooy, “Quantization and dither: A theoretical survey,” J. Ausio Eng. Soc., vol. 40, no. 5, pp. 355-375, May 1992.

[21]Chun-Hsien Su, “A fourth-order cascaded sigma-delta modulator with DAC nonlinearity cancellation techniques,” Ph. D. Dissertation, Texas Tech University, May 2004.

[22]S. Ardalan and J. Paulos, “An analysis of nonlinear behavior in delta-sigma modulators,” IEEE Trans. Circuits Syst., vol. CAS-34, pp. 593-603, Jun. 1987.

[23]E. Stikvoort, "Some remarks on the stability and performance of the noise shaper or sigma-delta modulator," IEEE Trans. Commun., vol. COM-36, no. 10, pp. 1157-1162, Oct. 1988.

[24]M. Aldajani and A. Sayed, “Stability analysis of an adaptive structure for sigma delta modulation,” Proc. IEEE ISCAS 2000, vol. 1, pp. 129-132, Dec. 2000.

[25]R. Schreier, “An empirical study of high-order single-bit delta-sigma modulators,” IEEE Trans. Circuits and Syst. II, vol. CAS-40, no. 8, pp. 461-466, Aug. 1993.

[26]S. Hein and A. Zakhor, “On the stability of sigma delta modulators,” IEEE Trans. Signal Proc., vol. 41, no. 7, pp. 2322-2348, Jul. 1993.

[27]R. Baird and T. Fiez, "Stability analysis of high-order delta-sigma modulator for ADC’s," IEEE Trans. Circuits and Syst. II, vol. CAS-41, no. 1, pp. 59-62, Jan. 1994.

[28]S. Hein and A. Zakhor, Sigma Delta Modulators: Nonlinear Decoding, Algorithms, and Stability Analysis, Chapter 7. Kluwer Academic Publishers, Nowell, MA, 1993.

[29]R. Adams, “The design of high-order signle-bit  ADCs,” : Delta-sigma data converters: Theory, design, and simulation, IEEE Press, New York, 1997.

[30]R. Schreier, and G. Temes, Understanding Delta-Sigma Data Converters, IEEE Press, New York, NY, 2005.

[31]Form Intel’s website, http://www.intel.com.

[32]D. B. Ribner et al., "A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealities," IEEE J. Solid-State Circuits, vol. SC-26, no. 12, pp. 1764-1774, Dec. 1991.

[33]O. Feely and L. Chua, “The effect of integrator leak in - modulation,” IEEE Trans. Circuits and Syst, vol. CAS-38, no. 11, pp. 1293-1305, Nov. 1991.

[34]C. Su and K. Chao, “A fourth-order cascaded sigma-delta modulator with DAC error cancellation technique,” IEEE Proc. 45th Midwest Symposium on Circuits and Systems, vol. 2, pp. 5-8, Aug. 2002.

[35]D. Cini, C. Samori, and A. L. Lacaita, “Double-index averaging: a novel technique for dynamic element matching in - A/D converters,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 353-358, Apr. 1999.

[36]Y. Matsuya, K. Uchimura, A. Iwata, and T. Kaneko, “A 17-bit oversampling D-to-A conversion technology using multistage noise shaping,” IEEE J. Solid-State Circuits, vol. SC-24, pp. 969-975, Aug. 1989.

[37]R. Schreier and B. Zhang, “Noise-shaped multibit D/A converter employing unit elements,” Electronic. Lett., pp. 1712-1713, Sep. 28, 1995.

[38]T. Shui, R. Schreier, and F. Hudson, “Mismatch shaping for a current-mode multi-bit delta-sigma DAC,” IEEE J. Solid-State Circuits, vol. SC-34, no. 3, pp. 331-338, Mar. 1999.

[39]F. Chen and B. Leung, “A high resolution multibit sigma-delta modulator with individual level averaging,” IEEE J. Solid-State Circuits, vol. SC-30, no.4, pp. 453-460, Apr. 1995.

[40]D. Cini, C. Samori, and A. L. Lacaita, “Double-index averaging: a novel technique for dynamic element matching in - A/D converters,” IEEE Trans. Circuits Syst. II, vol. 46, pp. 353-358, Apr. 1999.

[41]R. Baird and T. Fiez, “Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging,” IEEE Trans. Circuits Syst. II, vol. 42, pp. 753-762, Dec. 1995.

[42]R. Adams, K. Nguyen, and K. Sweetland, “A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling,” IEEE J. Solid-State Circuits, vol. SC-33, no. 12, pp. 1871-1878, Dec. 1998.

[43]K. Chen and K. Kuo, “An improved technique for reducing baseband tones in sigma-delta modulators employing data weighted averaging algorithm without adding dither,” IEEE Trans. Circuits and Syst. II, vol. CAS-46, no. 1, pp. 69-74, Jan. 1999.

[44]O. Nys and R. K. Henderson, “A 19-bit lower-power multibit sigma-delta ADC based on data weighted averaging,” IEEE J. Solid-State Circuits, vol. 32, pp. 933-942, Jul. 1997.

[45]R. Radke, A. Eshraghi, and T.S. Fiez, “A 19-bit current-mode  DAC based upon rotated data weighted averaging,” IEEE J. Solid-State Circuits, vol. SC-35, pp. 1074-1083, Aug. 2000.

[46]I. Fujimori, L. Lorenzo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao, and S. Chan, “A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8x oversampling ratio,” IEEE J. Solid-State Circuits, vol. 35, pp.1820-1828, Dec. 2000.

[47]E. Forleman, J. Welz, and I. Galton, “An audio ADC delta-sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC,” IEEE J. Solid-State Circuits, vol. SC-36, no. 3, pp. 339-348, Mar. 2001.

[48]E. Hogenauer, “An Economical Class of Digital Filters for Decimation,” IEEE Trans. on Acoustics, Speech, and Signal Processing, vol. ASSP-29, no. 2, pp. 155-162, Apr. 1981.

[49]R. Gregorian and. G. Temes, Analog MOS Integrated Circuits for Signal Processing, John Wiley & Sons Inc., New York, NY, 1986.

[50]M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, Oxford University Press, New York, NY, 2001.
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