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研究生:林于斌
研究生(外文):Yu-Bin Lin
論文名稱:植基於FPGA之回歸型最簡類化型小腦模型控制器之硬體實現
論文名稱(外文):Hardware Implementation of Recurrent S_CMAC_GBF Based on FPGA
指導教授:江青瓚
指導教授(外文):Ching-Tsan Chiang
學位類別:碩士
校院名稱:清雲科技大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:99
中文關鍵詞:回歸型最簡定址架構之類化型小腦模型控制器現場可規劃邏輯閘陣列時間序關聯性硬體實現
外文關鍵詞:RecurrentS_CMAC_GBFFPGATemporal RelevantHardware Implementation
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本文主要的研究目的是設計一回歸型最簡定址架構之類化型小腦膜型控制器(Recurrent Simple Addressing Structure for Cerebellar Model Articulation Controller with General Basis Function, Recurrent S_CMAC_GBF),並以現場可規劃邏輯閘陣列(Field Programmable Gate Array, FPGA)晶片實現之。最簡定址架構之類化型小腦模型控制器(S_CMAC_GBF)之學習收斂性與精確度皆優於類化型小腦模型控制器(CMAC_GBF),而Recurrent S_CMAC_GBF將原本S_CMAC_GBF的結構中加入回授的部份,使其成為時序關聯性之架構,並有能力去解決動態系統或時序關聯性問題,在此S_CMAC_GBF與Recurrent S_CMAC_GBF分別對靜態以及動態都有著顯著的效能,但卻受限於電腦的大小與輸入輸出之傳輸速度,因此應用與發展上有其限制。故本文將此系統縮小至IC晶片等級,進而增加系統的處理速度使得系統從毫秒等級提升至微秒等級。首先用Borland C軟體來驗證Recurrent S_CMAC_GBF對時間序關聯性範例之學習性能,接著以ALTERA Quartus II軟體且使用Verilog硬體描述語言,將本研究所設計的硬體架構進行硬體化之軟體模擬,最後透過FPGA系統晶片實現設計之硬體架構,並利用RS-232串列傳輸將學習後參數回傳至電腦以進行時間序關聯性範例之學習驗證。
This study is to design and develop the hardware structure of Recurrent S_CMAC_GBF, and to implement and test the hardware structure by using FPGA chip. S_CMAC_GBF has the same learning convergence characteristic as in CMAC_GBF, but with stronger system accuracy. The learning structure of recurrent enables S_CMAC_GBF with the ability to solve dynamic system or time relevant problem. Although S_CMAC_GBF and Recurrent S_CMAC_GBF have outstanding learning performances and applications in static and dynamic systems, both are restricted to the huge computer size and input/output speed, therefore, it is hard to expand their applications. This study reduces the system size to IC grade and increases the processing speed from sec to sec. First, the study uses Borland C software to prove Recurrent S_CMAC_GBF to temporal relevant examples of learning performances. Second, Recurrent S_CMAC_GBF hardware structure proceeds software simulation with ALTERA Quartus II software and Verilog hardware description language. Finally, using FPGA system chip implementation for Recurrent S_CMAC_GBF hardware structure, and the parameter through learning by RS-232 return to the computer to verify.
中文摘要..........................................................i
英文摘要.........................................................ii
誌謝............................................................iii
目錄.............................................................iv
圖目錄...........................................................vii
表目錄............................................................x
第一章 緒論........................................................1
1.1 研究背景與動機.................................................1
1.2 研究目的......................................................2
1.3 研究方法......................................................3
1.4 論文架構......................................................3
第二章 小腦模型控制器之理論探討......................................5
2.1 傳統小腦模型控制器(CMAC).......................................5
2.1.2 傳統小腦模型控制器之學習方式..................................9
2.1.3 相關之應用範例...............................................9
2.2 類化型小腦模型控制器(CMAC_GBF).................................11
2.2.1 基本架構....................................................11
2.2.2 類化型小腦模型控制器之學習方法................................14
2.3 最簡定址架構之類化型小腦模型控制器(S_CMAC_GBF)...................16
2.3.1 基本架構....................................................16
2.3.2 最簡定址架構類化型小腦模型控制器之學習方法......................17
2.3.3 最簡定址架構之類化型小腦模型控制器優缺點及應用..................18
2.4 結語.........................................................20
第三章 回歸型最簡定址架構之類化型小腦模型控制器之介紹..................22
3.1 回歸型最簡類化型小腦模型控制器(Recurrent S_CMAC_GBF)............22
3.1.1 架構設計...................................................22
3.1.2學習方法....................................................24
3.2 學習收斂性之證明..............................................25
3.3 軟體模擬.....................................................28
3.3.1 簡單之時序關聯性例子.........................................28
3.3.2 動態(dynamic)非線性系統.....................................30
3.4 結語.........................................................31
第四章 回歸型最簡定址架構之類化型小腦模型控制器硬體實現................33
4.1 硬體測試設備介紹..............................................33
4.1.1 Stratix II系列之FPGA實驗板.................................34
4.1.2 硬體測試設備連接............................................36
4.2 硬體架構設計.................................................37
4.2.1 參數記憶體模組(Parameters_RAMs).............................37
4.2.2 回歸模組(Recurrent Module).................................39
4.2.3 高斯函數產生器模組(GBF Generators)..........................40
4.2.4 乘加器模組(MAC)............................................41
4.3 硬體架構之程式設計............................................42
4.3.1 參數設定...................................................42
4.3.2 高斯函數的 值運算...........................................42
4.3.3 高斯函數的初始設定與查表法...................................43
4.3.4 輸出之運算.................................................44
4.4 硬體程式結合與實驗結果.........................................45
4.4.1 簡單之時序關聯性例子........................................47
4.4.2 動態非線性系統..............................................53
4.5 結語........................................................55
第五章 具學習能力之回歸型最簡定址架構類化型小腦模型控制器硬體實現.......59
5.1 具學習能力之硬體架構設計.......................................59
5.1.1參數記憶體模組(Parameters_RAMs)..............................60
5.1.2 回歸模組(Recurrent Module).................................61
5.1.3 高斯函數產生器模組(GBF Generators)..........................61
5.1.4 乘加器模組(MAC).............................................63
5.1.5 學習模組(Learning Module)..................................63
5.2 具學習能力之硬體程式設計.......................................66
5.2.1 初始值參數設定..............................................67
5.2.2 高斯函數的 值運算...........................................67
5.2.3 增加高斯函數解析度之初始設定與查表法...........................67
5.2.4 學習模組的運算參數(k_m, k_var, k_h)之計算....................68
5.3 硬體程式之結合與詳細說明.......................................69
5.3.1 硬體模組之詳細步驟說明.......................................71
5.3.2 軟體模擬...................................................81
5.3.3 硬體測試結果...............................................85
5.3.4 結語......................................................87
第六章 結論......................................................90
6.1 研究成果.....................................................90
6.2 研究問題與解決方法............................................90
6.3 研究心得.....................................................91
6.4 未來展望.....................................................92
參考文獻.........................................................93
附錄一...........................................................97
簡歷.............................................................99
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