臺灣博碩士論文加值系統

本文主要的研究目的是設計一回歸型最簡定址架構之類化型小腦膜型控制器(Recurrent Simple Addressing Structure for Cerebellar Model Articulation Controller with General Basis Function, Recurrent S_CMAC_GBF)，並以現場可規劃邏輯閘陣列(Field Programmable Gate Array, FPGA)晶片實現之。最簡定址架構之類化型小腦模型控制器(S_CMAC_GBF)之學習收斂性與精確度皆優於類化型小腦模型控制器(CMAC_GBF)，而Recurrent S_CMAC_GBF將原本S_CMAC_GBF的結構中加入回授的部份，使其成為時序關聯性之架構，並有能力去解決動態系統或時序關聯性問題，在此S_CMAC_GBF與Recurrent S_CMAC_GBF分別對靜態以及動態都有著顯著的效能，但卻受限於電腦的大小與輸入輸出之傳輸速度，因此應用與發展上有其限制。故本文將此系統縮小至IC晶片等級，進而增加系統的處理速度使得系統從毫秒等級提升至微秒等級。首先用Borland C軟體來驗證Recurrent S_CMAC_GBF對時間序關聯性範例之學習性能，接著以ALTERA Quartus II軟體且使用Verilog硬體描述語言，將本研究所設計的硬體架構進行硬體化之軟體模擬，最後透過FPGA系統晶片實現設計之硬體架構，並利用RS-232串列傳輸將學習後參數回傳至電腦以進行時間序關聯性範例之學習驗證。

This study is to design and develop the hardware structure of Recurrent S_CMAC_GBF, and to implement and test the hardware structure by using FPGA chip. S_CMAC_GBF has the same learning convergence characteristic as in CMAC_GBF, but with stronger system accuracy. The learning structure of recurrent enables S_CMAC_GBF with the ability to solve dynamic system or time relevant problem. Although S_CMAC_GBF and Recurrent S_CMAC_GBF have outstanding learning performances and applications in static and dynamic systems, both are restricted to the huge computer size and input/output speed, therefore, it is hard to expand their applications. This study reduces the system size to IC grade and increases the processing speed from sec to sec. First, the study uses Borland C software to prove Recurrent S_CMAC_GBF to temporal relevant examples of learning performances. Second, Recurrent S_CMAC_GBF hardware structure proceeds software simulation with ALTERA Quartus II software and Verilog hardware description language. Finally, using FPGA system chip implementation for Recurrent S_CMAC_GBF hardware structure, and the parameter through learning by RS-232 return to the computer to verify.

中文摘要..........................................................i
英文摘要.........................................................ii
誌謝............................................................iii
目錄.............................................................iv
圖目錄...........................................................vii
表目錄............................................................x
第一章 緒論........................................................1
1.1 研究背景與動機.................................................1
1.2 研究目的......................................................2
1.3 研究方法......................................................3
1.4 論文架構......................................................3
第二章 小腦模型控制器之理論探討......................................5
2.1 傳統小腦模型控制器(CMAC).......................................5
2.1.2 傳統小腦模型控制器之學習方式..................................9
2.1.3 相關之應用範例...............................................9
2.2 類化型小腦模型控制器(CMAC_GBF).................................11
2.2.1 基本架構....................................................11
2.2.2 類化型小腦模型控制器之學習方法................................14
2.3 最簡定址架構之類化型小腦模型控制器(S_CMAC_GBF)...................16
2.3.1 基本架構....................................................16
2.3.2 最簡定址架構類化型小腦模型控制器之學習方法......................17
2.3.3 最簡定址架構之類化型小腦模型控制器優缺點及應用..................18
2.4 結語.........................................................20
第三章 回歸型最簡定址架構之類化型小腦模型控制器之介紹..................22
3.1 回歸型最簡類化型小腦模型控制器(Recurrent S_CMAC_GBF)............22
3.1.1 架構設計...................................................22
3.1.2學習方法....................................................24
3.2 學習收斂性之證明..............................................25
3.3 軟體模擬.....................................................28
3.3.1 簡單之時序關聯性例子.........................................28
3.3.2 動態(dynamic)非線性系統.....................................30
3.4 結語.........................................................31
第四章 回歸型最簡定址架構之類化型小腦模型控制器硬體實現................33
4.1 硬體測試設備介紹..............................................33
4.1.1 Stratix II系列之FPGA實驗板.................................34
4.1.2 硬體測試設備連接............................................36
4.2 硬體架構設計.................................................37
4.2.1 參數記憶體模組(Parameters_RAMs).............................37
4.2.2 回歸模組(Recurrent Module).................................39
4.2.3 高斯函數產生器模組(GBF Generators)..........................40
4.2.4 乘加器模組(MAC)............................................41
4.3 硬體架構之程式設計............................................42
4.3.1 參數設定...................................................42
4.3.2 高斯函數的 值運算...........................................42
4.3.3 高斯函數的初始設定與查表法...................................43
4.3.4 輸出之運算.................................................44
4.4 硬體程式結合與實驗結果.........................................45
4.4.1 簡單之時序關聯性例子........................................47
4.4.2 動態非線性系統..............................................53
4.5 結語........................................................55
第五章 具學習能力之回歸型最簡定址架構類化型小腦模型控制器硬體實現.......59
5.1 具學習能力之硬體架構設計.......................................59
5.1.1參數記憶體模組(Parameters_RAMs)..............................60
5.1.2 回歸模組(Recurrent Module).................................61
5.1.3 高斯函數產生器模組(GBF Generators)..........................61
5.1.4 乘加器模組(MAC).............................................63
5.1.5 學習模組(Learning Module)..................................63
5.2 具學習能力之硬體程式設計.......................................66
5.2.1 初始值參數設定..............................................67
5.2.2 高斯函數的 值運算...........................................67
5.2.3 增加高斯函數解析度之初始設定與查表法...........................67
5.2.4 學習模組的運算參數(k_m, k_var, k_h)之計算....................68
5.3 硬體程式之結合與詳細說明.......................................69
5.3.1 硬體模組之詳細步驟說明.......................................71
5.3.2 軟體模擬...................................................81
5.3.3 硬體測試結果...............................................85
5.3.4 結語......................................................87
第六章 結論......................................................90
6.1 研究成果.....................................................90
6.2 研究問題與解決方法............................................90
6.3 研究心得.....................................................91
6.4 未來展望.....................................................92
參考文獻.........................................................93
附錄一...........................................................97
簡歷.............................................................99

[1]江堆金，張嘉展，SoC開發實戰：使用Verilog，學貫行銷，台北市，民國九十三年。
[2]范逸之，陳立元，Visual Basic與RS-232串列通訊控制最新版，文魁資訊，台北市，民國九十年。
[3]鄭信源，Verilog硬體描述語言數位電路，二版，儒林圖書公司，台北市，民國八十九年。
[4]楊文傑，「使用模糊小腦模型連結控制器及FPGA實現交流馬達解耦的定子磁通及轉矩成分」，明志科技大學，碩士論文，民國九十六年。
[5]龔書暉，「內嵌內容可定址記憶體之CMAC控制器」，中正大學，碩士論文，民國九十年。
[6]A. Savran, “Multifeedback-Layer Neural Network,” IEEE Transactions on Neural Networks, Vol. 18, No. 3, pp. 373-384, 2007.
[7]C. F. Juang and C. T. Lin, “A Recurrent Self-Organizing Neural Fuzzy Inference Network,” IEEE Transactions on Neural Networks, Vol. 10, No. 4, pp. 828-845, 1999.
[8]C. S. Lin and C. K. Li, “A Sum-of-Product Neural Network (SOPNN),” Neurocomputing, Vol. 30, pp. 273-291, 2000.
[9]C. S. Lin and C. T. Chiang, “Learning Convergence of CMAC Technique,” IEEE Transactions on Neural Networks, Vol. 8, No. 6, pp. 1281-1292, 1997.
[10]C. T. Chiang and C. M. Chong, “Hardware Implementation of a Simple Structure of Addressing Technique for CMAC_GBF,” IEEE International Symposium on Industrial Electronics, Vol. 1, pp. 139-144, 2005.
[11]C. T. Chiang and C. S. Lin, “Integration of CMAC and Radial Basis Function Techniques,” IEEE International Conference on Intelligent Systems for the 21st, Vol. 4, pp. 3263-3268, 1995.
[12]C. T. Chiang and C. S. Lin, “CMAC with General Basis Functions.” Journal of Neural Networks, Vol. 9, No. 7, pp. 1199-1211, 1996.
[13]C. T. Chiang, T. S. Chiang and C. K. Li, “A Simple and Converged Structure of Addressing Technique for CMAC_GBF,” 2004 IEEE International Conference on Systems, Man and Cybernetics, pp. 6097-6101, 2004.
[14]C. T. Chiang and T. S. Chiang, “A Converged Recurrent Structure for CMAC_GBF and S_CMAC_GBF,” IEEE International Symposium on Industrial Electronics, pp. 1876-1881, 2007.
[15]D. Marr, “A Theory of Cerebellar Cortex,” J. Physiol, Vol. 202, pp. 437-470, 1969.
[16]D. S. Reay, T. C. Green and B. W. Williams, “Field Programmable Gate Array Implementation of A Neural Network Accelerator,” IEE Colloquium on Hardware Implementation of Neural Networks and Fuzzy Logic, pp. 2/1-2/3, 1994.
[17]F. O. Rodriguez, W. Yu and M. A. Moreno-Armendariz, “Nonlinear Systems Identification Via Two Types of Recurrent Fuzzy CMAC,” IEEE International Joint Conference on Neural Networks, pp. 823-828, 2007.
[18]J. C Jan and S. L. Hung, “High-Order MS-CMAC Neural Network,” IEEE Transactions on Neural Networks, Vol. 12, No. 3, pp. 598-603, 2001.
[19]J. S. Albus, “A New Approach to Manipulator Control: The Cerebellar Model Articulation Controller (CMAC),” Journal of Dynamic System, and Control, Transaction of ASME, pp. 220-227, 1975.
[20]J. S. Albus, “Data Storage in the Cerebellar Model Articulation Controller (CMAC),” Journal of Dynamic Systems, Measurement and Control, Transaction of ASME, pp. 228-233, 1975.
[21]J. S. Ker, Y. H. Kuo, R. C. Wen and B. D. Liu, “Hardware Implementation of CMAC Neural Network with Reduced Storage Requirement,” IEEE Transactions on Neural Networks, Vol. 8, No. 6, pp. 1545-1556, 1997.
[22]L. Weruaga and B. Kieslinger, “Tikhonov Training of the CMAC Neural Network,” IEEE Transactions on Neural Networks, Vol. 17, No. 3, pp. 613-622, 2006.
[23]M. Miwa, “Cerebellar Model Arithmetic Computer with Bacterial Evolutionary Algorithm and Its Hardware Acceleration Using FPGA,” IEEE International Conference on Systems, Man, and Cybernetics, Vol. 5, pp. 591-595, 1999.
[24]M. Miwa, “CMAC Modeling Using Bacterial Evolutionary Algorithm (BEA) on Field Programmable Gate Array (FPGA),” Industrial Electronics Society, 2000. IECON2000. 26th Annual Conference of the IEEE, Vol. 1, pp. 644-650, 2000.
[25]N. Sadati, M. Bagherpour and R. Ghadami, “Adaptive Multi-Model Controller for Robotic Manipulators Based on CMAC Neural Networks,” IEEE International Conference on Industrial Technology, pp. 1012-1017, 2005.
[26]P. A. Mastorocostas and J. B. Theocharis, “A Recurrent Fuzzy-Neural Model for Dynamic SystemIdentification,” IEEE Transactions on Systems, Man, and Cybernetics, Vol. 32, No. 2, pp. 176-190, 2002.
[27]P. S. Sastry, G. Santharam and K. P. Unnikrishnan, “Memory Neural Networks for Identification and Control of Dynamical Systems,” IEEE Transactions on Neural Networks, Vol. 5, No. 2, pp. 306-319, 1994.
[28]R. J. Wai, C. M. Lin and Y. F. Peng, “Robust CMAC neural network control for LLCC-resonant driving linear piezoelectric ceramic motor,” IEE Proceedings Contr. Theory Applications., Vol. 150, No. 3, pp. 221-232, 2003.
[29]S. H. Lane, D. A. Handelman and J. J. Gelfand, “Theory and Development of Higher-Order CMAC Neural Networks,” IEEE Control System, Vol. 12, pp. 23-30, 1992.
[30]S. Santini, A. D. Bimbo and R. Jain, “Block-Structured Recurrent Neural Networks,” Neural Networks, Vol. 8, No. 1, pp. 135-147, 1995.
[31]W. T. Miller, F. H. Glanz and L. G. Kraft, “Application of a General Learning Algorithm to the Control of Robotics Manipulators,” The International Journal of Robotics Research, Vol. 6, No. 2, pp. 84-98, 1987.
[32]W. T. Miller, F. H. Glanz and L. G. Kraft, “CMAC: An Associative Neural Network Alternative to Backpropagation,” Proceedings of the IEEE, Vol. 78, No. 10, pp. 1561-1567, 1990.
[33]W. T. Miller, “Real-Timer Neural Network Control of A Biped Walking Robot,” IEEE Control Systems Magazine, Vol. 14, No. 1, pp. 41-48, 1994.
[34]Y. H. Kim and F. L. Lewis, “Optimal Design of CMAC Neural-Network Controller for Robot Manipulators,” IEEE Transactions on Systems, Man, and Cybernetics, Vol. 30, No. 2, pp. 22-31, 2000.
[35]Y. Iiguni, “Hierarchical Image Coding via Cerebeller Model Arithmetic Computers”, IEEE Transactions on Image Processing, Vol. 5, No. 10, pp. 1393-1401, 1996.