臺灣博碩士論文加值系統

在此篇論文中，我們提出一個高效率的上提式5/3濾波器之二維離散小波轉換架構。使用移位器取代原本的乘法器來達到乘於預測與更新的係數以完成上提式步驟。移位的方法能夠節省硬體面積跟計算複雜度。另外，我們加入了一顆多工器來減少硬體資源，藉著使用移位器、多工器與摺疊式方法使此架構能實現於多階離散小波轉換來達到高硬體使用率。
最後以Verilog HDL描述我們提出的電路架構，經過編譯模擬完成後，再利用Xilinx的元件庫設計。我們使用Xilinx FPGA的晶片為Spartan II XC 2S200-5PQ208C，透過這顆晶片來模擬實現我們所設計的電路。

In this paper, an efficient architecture is proposed for realization of 2D lifting-based 5/3 filter discrete wavelet transform (DWT). By substituting multipliers, it is a better choice to adopt shifters for the realization of lifting computation with the predictor/update coefficient. Such a shifter approach is able to save the hardware area and computation load. In addition, an extra multiplexer is employed here for the hardware cost reduction. By using shifters and multiplexer, based on the folding scheme, the architecture is proposed for the realization of multilevel wavelet transform with the higher hardware utilization. Finally, by employing Matlab/Simulink simulation, the proposed architecture can achieve pretty high PSNR quality of reconstructed images, and then the result shows the efficacy of the architecture. Then, we implement them on a FPGA device of Spartan II XC 2S200-5PQ208C.

目錄
中文摘要 I
Abstract II
誌 謝 III
目錄 IV
表目錄 VII
圖目錄 VIII
第一章 緒論 1
1.1 研究動機 1
1.2 相關研究 2
1.3 各章節提要 3
第二章 離散小波轉換 5
2.1 前言 5
2.2 傳統離散小波轉換 6
2.3 上提式離散小波轉換 9
2.3.1 上提式離散小波正轉換 9
2.3.2上提式離散小波反轉換 11
2.3.3與傳統離散小波之比較 12
2.4 一維三階離散小波轉換 13
2.5 二維離散小波轉換 14
2.5.1 二維一階離散小波轉換 14
2.5.2 二維三階離散小波轉換 17
第三章 5/3濾波器之二維上提式離散小波轉換架構 19
3.1 前言 19
3.2 設計概念 19
3.2.1 以移位器取代乘法器 19
3.2.2 二維影像之設計概念 21
3.2.3加入Multiplexer設計 21
3.2.4 列轉換 23
3.2.5 行轉換 24
3.2.6 反轉換架構 26
3.3 多階的設計 28
3.4 上提式5/3濾波器係數架構之硬體實現 28
3.5 數學模擬驗證 30
3.6 上提式DWT的HDL語言模擬 31
第四章 模擬與結果 34
4.1 前言 34
4.2 設計流程 34
4.3 硬體實現 36
4.3.1 設計流程 36
4.3.2 FPGA Demo Board 39
4.3.3電腦端與 FPGA 硬體連線 40
4.4 效能與結果 42
第五章 結論與未來展望 50
參考文獻 52
附錄 54
附錄A：RS232 54
附錄B：Xilinx-ISE 8.1i晶片設計環境簡介 55
附錄C：晶片實作 56
附錄D：部份RTL Code 70

表目錄
表2.1 硬體資源比較表..................................................................................... 12
表2.2 5/3 濾波器各階係數表............................................................................ 18
表3.1 5/3 濾波器係數處理方式表.................................................................... 21
表4.1 影像重建後PSNR 表............................................................................. 42
表4.2 二維一階上提式硬體資源比較表......................................................... 42
表4.3 使用的硬體資源和性能表..................................................................... 43
表4.4 離散小波正轉換合成結果表................................................................. 43

圖目錄
圖2. 1 輸入資料與高低頻係數的關係.............................................................. 7
圖2. 2 一階一維離散小波轉換之正、反轉換架構圖...................................... 8
圖2. 3 上提式離散小波正轉換架構.................................................................. 9
圖2. 4 上提式離散小波反轉換架構................................................................ 11
圖2. 5 一維三階離散小波轉換架構架構圖.................................................... 13
圖2. 6 二維ㄧ階離散小波轉換執行方向圖.................................................... 15
圖2. 7 二維ㄧ階離散小波轉換示意圖............................................................ 16
圖2. 8 二維ㄧ階離散小波正轉換架構圖........................................................ 16
圖2. 9 二維ㄧ階離散小波反轉換架構圖........................................................ 17
圖2. 10 二維三階離散小波轉換架構圖.......................................................... 18
圖3. 1 直接式二維ㄧ階離散小波轉換架構圖................................................ 22
圖3. 2 二維ㄧ階離散小波轉換架構圖............................................................ 22
圖3. 3 改良後5/3 濾波器之上提式離散小波正轉換硬體架構.................... 24
圖3. 4 列方向小波轉換示意圖........................................................................ 24
圖3. 5 行方向小波轉換示意圖........................................................................ 25
圖3. 6 5/3 濾波器之1-D 上提式離散小波正轉換計算時序.......................... 25
圖3. 7 轉置記憶體的編排圖............................................................................ 26
圖3. 8 5/3 濾波器之1-D 上提式離散小波反轉換計算時序.......................... 27
圖3. 9 改良後5/3 濾波器之上提式離散小波反轉換硬體架構.................... 27
圖3. 10 二維多階離散小波轉換架構圖.......................................................... 28
圖3. 11 5/3 濾波器之上提式離散小波轉換架構............................................. 29
圖3. 12 5/3 濾波器之上提式離散小波轉換架構程式區塊圖........................ 29
圖3. 13 二維一階離散小波轉換ModelSim 輸入資料示意圖....................... 32
圖3. 14 二維一階離散小波轉換ModelSim 輸出資料示意圖....................... 32
圖3. 15 二維一階離散小波正轉換RTL 合成電路圖.................................... 33
圖3. 16 二維一階離散小波反轉換RTL 合成電路圖.................................... 33
圖4. 1 不同層級的電路示意圖........................................................................ 35
圖4. 2 電路架構設計流程圖............................................................................ 36
圖4. 3 FPGA 設計流程圖.................................................................................. 37
圖4. 4 離散小波轉換流程圖............................................................................ 38
圖4. 5 DEMO BOARD 實際照片..................................................................... 39
圖4. 6 DEMO BOARD 版面配置圖................................................................. 39
圖4. 7 ISE 合成TOP 電路圖............................................................................ 42
圖4. 8 正轉換VB 結果圖................................................................................ 46
圖4. 9 反轉換VB 結果圖................................................................................ 46
圖4. 10 轉換後的影像結果.............................................................................. 46
圖A. 1 RS232 修改圖........................................................................................ 54
圖B. 1 ISE 8.1i 主畫面...................................................................................... 55

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