臺灣博碩士論文加值系統

本論文將針對應用於整合型面板的閘極驅動電路可靠度提升進行
研究，本論文以整合於TFT 面板上之閘極驅動電路為基礎，研究並加以修正電路以提高閘驅動電路的可靠度。本論文使用的方法有兩項：首先參考雙電位下拉結構(Dual Pull-Down Structure)以雙倍電路來分擔傳統電路中部分長時間工作之迴路中電晶體的負荷，達到延緩電晶體老化的速率，減輕關鍵電晶體所受的應力效應(Stress Effect)。再者以變更控制訊號後可以得到有效的減低Stress Effect的影響,並可以提高閘極驅動電路的可靠性。
本論文將針對放電路徑應用於整合型閘極驅動電路中所需的設計考量進行討論，有關軟體部分則使用Hspice 進行電路模擬、利用Laker 從事電路佈局，並使用TSMC2P4M 0.35μm 製程技術進行實現與驗證。

In this thesis, base on the conventional gate driver circuit integrated on TFT-LCD panels, improvement of the reliability of the gate drivers on the integrated TFT-LCD panels was investigated. There were two approaches used in our investigation. First, the dual pull-down structure was involved in the gate driver circuit. In this tructure, two pull-down transistors were used to replace the long-duty transistor in the conventional driver. Each pull-down transistor has only half of working duty such that the degeneration will be retarded, and the lifetime of the circuit will be promoted. In addition to change the control signals can be effectively reduce the impact of Stress Effect, and to increase gate drive circuit reliability.
This thesis will focus on the design of the TFT gate driver integrated on TFT-LCD panels. And the optimal way to control the discharging was also searched.

總目錄
誌謝-------------------------------------------------------------------------------------I
中文摘要------------------------------------------------------------------------------II
Abstract------------------------------------------------------------------------------ III
總目錄--------------------------------------------------------------------------------IV
圖目錄------------------------------------------------------------------------------- VI
表目錄---------------------------------------------------------------------------------X
第一章 緒論--------------------------------------------------------------------------1
1.1 液晶顯示器簡介--------------------------------------------------------------1
1.2 TFT-LCD 系統介紹-------------------------------------------------------13
1.3.1 TFT-LCD 驅動原理-------------------------------------------------------18
1.3.2 反轉驅動法----------------------------------------------------------------21
1.4 研究動機----------------------------------------------------------------------24
1.5 論文架構----------------------------------------------------------------------25
第二章 TFT 閘極驅動電路-------------------------------------------------------26
2.1 TFT 閘極驅動電路設計考量----------------------------------------------28
2.2 傳統TFT 閘極驅動電路---------------------------------------------------30
2.3 傳統TFT 閘極驅動電路模擬結果---------------------------------------34
2.4 結論---------------------------------------------------------------------------36
第三章 雙電位下拉結構之TFT 閘極驅動電路設計-------------------------37
3.1 雙電位下拉結構之TFT 閘極驅動電路設計考量----------------------37
3.2 雙電位下拉結構之TFT 閘極驅動電路---------------------------------37
3.3 模擬結果---------------------------------------------------------------------42
3.4 結論----------------------------------------------------------------------------45
第四章改良式TFT Dual Pull Down 閘極驅動電路設計--------------------46
4.1 改良式TFT Dual Pull Down 閘極驅動電路設計考量---------------46
4.2 輸入控制訊號設計---------------------------------------------------------46
4.3 改良式TFT 閘極驅動電路-------------------------------------------------52
第五章電路可靠度增加設計與討論--------------------------------------------60
5.1 解決電容耦合---------------------------------------------------------------60
5.2 討論---------------------------------------------------------------------------65
5.3 電路佈局---------------------------------------------------------------------66
第六結論-----------------------------------------------------------------------------67
參考文獻-----------------------------------------------------------------------------68
附錄-----------------------------------------------------------------------------------71

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