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研究生:蔡明倩
研究生(外文):Ming-Chien Tsai
論文名稱:SoC晶片中多重電壓與頻率IPs核心之高解析度功能速度自我分類機制
論文名稱(外文):Functiional Self High-Precision Speed-Binning Mechanism for IP Cores with Multi-Voltage and Multi-Clock in SoC Chip
指導教授:鄭經華
指導教授(外文):Ching-Hwa Cheng
學位類別:碩士
校院名稱:逢甲大學
系所名稱:電子工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:96
中文關鍵詞:延遲錯誤測試內嵌自我測試功能速度自我分類
外文關鍵詞:BISTDelay Fault TestingFunctiional Self Speed-Binning Mechanism
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隨著積體電路(VLSI)製程與設計技術的演進,電路設計逐漸趨向高速與單晶片系統(SoC)的方向發展,使得電路內部複雜度大幅地提升,同時對於電路的測試也面臨到空前的挑戰。因內部電路的輸出入不易直接從SoC電路外部的輸出入控制與測量,使得對於電路的測試複雜度提高且測試成本居高不下。現今利用外部測試機台(Automation Test Equipment;ATE)的測試方法也因為成本過高及機台本身精確性不高的因素下,因此本論文的測試環境將建構在無線測試平台上,以解決傳統測試平台的困境。藉由無線傳輸機台機制完成對晶片的測試,來降低現行昂貴測試機台(ATE)的成本與複雜度,已成為未來SoC測試主要之趨勢。
有別於一般傳統極速掃描延遲測試(At-Speed Testing)技術,本論文利用了Functional Delay Testing原理,以較低速的頻率提供測試圖樣(Test Patterns),再利用本論文所設計的邊緣調整電路對待測電路(CUT)量測延遲的錯誤(Delay Fault)。本論文主要現實了此極速掃描延遲測試(At-Speed Testing)技術在不同頻率與電壓之IP下進行測試。對於不同頻率與電壓的IP測試,本論文主要提出以動態電路中的真單相時脈方式(True Single Phase Clocking;TSPC)方式設計其IP之間的資料傳輸介面,可在資料傳輸中同時解決不同電壓的問題。且在介面電路中包含了交握(Handshaking)機制,以確保資料在不同時脈傳送的完整性。
VLSI’s process and design technology advances have been developed to have high speed and System-on-a-Chip (SoC). However, the complexity of circuit design has increased, and the circuit testing has new challenges. It is very difficult to control and test internal circuit from the input and output of SoC. We consider that the external ATE (Automation Test Equipment) has high cost, high test complexity, and inaccuracy. Therefore, this thesis uses wireless-testing platform to solve ATE’s traditional drawback. We achieve testing the chip by wireless-testing mechanism. This method decreases ATE’s cost, and it will become the main SoC testing technique in the future.
It is different for traditional at-speed testing, this thesis apply Functional Delay Testing technique to supply test patterns by slower frequency. We designed a clock edge tuning circuit to measure the delay fault in CUT (Circuit Under Test). Our target is realizing at-speed testing IP cores with multi-voltage and multi-frequency. The thesis presents the dynamic TSPC (True Single Phase Clocking) technique for the interface of data transmission in multi-voltage and multi-frequency IP cores. This method also solves data transmission problems in multi-voltage. Our interface adopts a handshaking mechanism, guaranteeing that there is no data loss when communication is done between two different clock domains.
中文摘要 i
ABSTRACT ii
誌謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章 序論 1
1.1 研究動機 1
1.2 論文研究方向與重點 4
1.3 論文章節安排 5
第二章 相關背景研究 6
2.1 無線測試(Wireless Testing)技術 6
2.2 非掃描延遲測試(Non-Scan Delay Testing) 7
2.1.1 Slow-Fast-Slow Delay Testing 7
2.1.2 極速掃描延遲測試(At-Speed Testing) 8
2.3 掃描延遲測試(Scan Based Delay Testing) 9
2.2.1 Launch-Off Shift Delay Testing 10
2.2.2 Launch-Off Capture Delay Testing 12
2.4 Speed Binning 13
2.5 非同步儲存單元(Asynchronous Storage Unit;ASU) 18
2.6 Globally-Asynchronous Locally-Synchronous (GALS) 18
2.7 時脈除頻之同步介面 19
2.8 半同步之介面 20
第三章 不同頻率與電壓之IP延遲測試技術 21
3.1 極速掃描延遲測試(At-Speed Scan Delay Testing)原理 22
3.2 內嵌式極速掃描延遲測試(Built-in At-Speed Self Delay Testing) 24
3.3 無線測試平台(Wireless Testing Platform) 25
3.4 極速掃描延遲測試之控制電路(CTL) 27
3.5 邏輯自我測試(Logic BIST) 28
3.5.1 測試圖樣產生器(Test Pattern Generation;TPG) 32
3.5.2 待測電路(Circuit Under Test ; CUT) 34
3.5.3 輸出結果分析器(Output Response Analysis;ORA) 36
3.6 動態真單相時脈方式(True Single Phase Clocking;TSPC)之介面 37
3.7 交握機制(Handshaking Mechanism) 45
3.8 測試時脈選擇器(Test Clock Select) 46
3.9 數位控制脈衝波產生器(Digital Controlled Pulse Generator;DCPG) 49
3.10 二進位搜尋電路(Binary Search Circuit) 51
3.11 內建自我延遲量測電路(Built-in Delay Measurement;BIDM) 52
3.12 資料儲存機制(Data Storage) 55
3.13 內嵌延遲元件(Inserted Delay Element) 56
第四章 設計流程 58
第五章 實驗結果與分析 61
5.1 數位控制脈衝波產生器(Digital Controlled Pulse Generator;DCPG) 61
5.2 二進位搜尋電路(Binary Search Circuit)之模擬 73
5.3 內建自我延遲量測電路(BIDM)之實驗結果 74
5.4 動態真單相時脈方式(TSPC)介面之實驗結果 75
5.5 內建自我測試(BIST)之整合實驗結果 77
5.6 CTL、Binary、Storage、DCPG及BIDM之整合 78
5.7 DUT之整合模擬 81
5.8 晶片測試計畫(Chip Test Plan) 82
第六章 結論與未來研究方向 84
參考文獻 85
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[4] P.-K Chen, Y.-T. Hsing, C.-W. Wu, “On Feasibility of HOY – A Wireless Test Methodology for VLSI Chips and Wafers,” in Proc. VLSI Design, Automation and Test Symp.(VLSI-DAT) ,pp. 1-4,Apr.2006
[5] 葉有偉, “A New Low-Power All Digital Pulsewidth-Locked-Loop,” 中正大學電機工程學系碩士論文
[6] 楊秋茂, “Design a Built-in Circuit Delay Self Testing Methodology,” 逢甲大學 產業碩士專班碩士論文
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[8] S. Ghosh, S. Bhunia, A. Raychowdhury and K. Roy,”Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor,” in Proc. Proceedings of the 12th IEEE International Symp. on On-Line Testing(IOLTS’06)
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[16] Sathe, V.; Ziesler, C.; Papaefihymiou, M.; Kinfl, S. and Kosonocky, S., “A synchronous interface for SoCs with multiple clock domains,” pages 173-174, Sept. 2004.
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