臺灣博碩士論文加值系統

本論文設計一個6位元快閃式類比數位轉換器，其目標為建構一回應表面模型(Response Surface Method)，穏健設計一具低功率消耗之快閃式類比數位轉換器。利用HSPICE電路模擬軟體，使用實驗設計 (Design Of Experiment)、基因演算法 (Genetic Algorithm) 以及加權組合回應表面模型 (Weighted Composite Response Surface Method) 之輔助，該加權組合回應表面模型用來決定類比數位轉換器其功率消耗與無雜散動態範圍之間的取捨關係。6位元快閃式類比數位轉換器使用TSMC 0.35�慆 2P4M 製程的模擬結果，積分非線性誤差為−0.67LSB ~ +0.06LSB，微分非線性誤差為−0.07LSB ~ +0.45LSB，輸入4.5166MHz的正弦波時，電路的無雜訊動態範圍 (SFDR) 為38.4474dB，總功率消耗為39.8858mW、晶片總面積為0.61mm×0.96mm。

In this thesis, we design a 6-bit Flash analog-to-digital converter (Flash ADC). A Response Surface Method (RSM) model for an analog to digital converter with low dissipation power. With the aid of HSPICE circuit simulation software, Design of Experiment (DOE), the Genetic Algorithm (GA) and Weighted Composite Response Surface Method (WCR), this RSM model can be used to make a decision in the tradeoff between the spurious free dynamic range (SFDR) and the dissipation power of the analog to digital converter. The simulation results of 6-bit flash ADC using the TSMC 0.35�慆 2P4M technology are as follows: the integral nonlinearity (INL) is −0.67LSB ~ +0.06LSB, the differential nonlinearity (DNL) is −0.07LSB ~ +0.45LSB, the spurious free dynamic range (SFDR) is about 38.4474dB for an input signal of 4.5166MHz sine wave, the total power dissipation is 39.89mW and the chip area is 0.61mm × 0.96mm with I/O pad.

目錄
摘要.................................................i
Abstract............................................ii
致謝...............................................iii
目錄................................................iv
圖目錄.............................................vii
表目錄...............................................x
第一章 序論.........................................01
1.1 研究背景........................................01
1.2 研究動機........................................02
1.3 論文架構........................................03
第二章 類比數位轉換器之架構.........................05
2.1 前言............................................05
2.2 類比數位轉換器..................................05
2.3 類比數位轉換器之架構介紹........................06
2.3.1快閃式類比數位轉換器...........................06
2.3.2 兩階段式類比數位轉換器........................08
2.3.3 管線式類比數位轉換器..........................10
2.4 類比數位轉換器之特性參數........................12
2.4.1 最低有效位元 .................................12
2.4.2 取樣率........................................13
2.4.3 無雜訊動態範圍................................13
2.4.4 微分非線性誤差................................13
2.4.5 積分非線性誤差................................15
2.5 結語............................................15
第三章 電路設計與模擬結果...........................16
3.1 前言............................................16
3.2 電壓比較器設計..................................17
3.3 數位編碼器之設計................................22
3.4 數位類比轉換器之模擬結果........................28
第四章 分析流程.....................................32
4.1 引言............................................32
4.2 表面回應方法....................................33
4.2.1 設定因子......................................34
4.2.2 建立Box-Behnken 矩陣實驗 .....................35
4.2.3 使用多元回歸分析建立表面回應方程式............37
第五章 最佳化設計...................................42
5.1 基因演算法......................................42
5.2 基本架構........................................43
5.2.1 基因編碼......................................44
5.2.2 適應函式......................................46
5.2.3 複製..........................................46
5.2.4 交配..........................................47
5.2.5 突變..........................................50
5.2.6 終止搜尋......................................50
5.3 基因演算法的特性................................51
5.4 使用基因演算法最佳化設計快閃式類比數位轉換器....52
5.5 加權式組合反應分析..............................54
5.6 結果比較與討論..................................56
5.7 量測考量........................................60
第六章 結論與未來工作...............................76
參考文獻............................................78


圖目錄
圖1 .1 類比數位轉換器應用之示意圖...................02
圖2.1 理想類比數位轉換器............................05
圖2.2 快閃式類比數位轉換器之方塊架構圖..............08
圖2.3 兩階段式類比數位轉換器之方塊架構圖............10
圖2.4 管線式類比數位轉換器之方塊架構圖..............12
圖2.5 類比數位轉換器之轉移曲線......................14
圖3.1 電壓比較器之基本運算..........................17
圖3.2 理想的輸出轉移特性............................17
圖3.3 本篇論文之電壓比較器電路圖....................20
圖3.3.1 電壓比較器之模擬結果........................20
圖3.4 Abed [11] 所提出的數位編碼器..................24
圖3.5 本論文之One-out-of-N電路圖....................24
圖3.6 本論文之數位編碼器............................25
圖3.7 數位編碼器之輸出模擬結果......................26
圖3.8 ADC之暫態模擬 @ fin=1Mhz......................28
圖3.9 還原ADC之輸出波形.............................28
圖3.10 ADC之FFT轉換頻譜模擬圖.......................29
圖3.11 ADC之直流分析模擬結果........................29
圖4.1 表面回應法流程圖..............................33
圖5.1 基因演算法之流程..............................43
圖5.2 基因演算法之基本單元..........................44
圖5.3 單點交配......................................47
圖5.4 雙點交配......................................48
圖5.5 均勻交配......................................48
圖5.6 功率消耗最佳化各因子準位結果..................60
圖5.7 SFDR最佳化各因子準位結果......................61
圖5.8 WCR最佳化各因子準位結果.......................61
圖5.9 功率消耗之P值檢定.............................62
圖5.9.1 功率消耗之響應期望圖........................62
圖5.10 SFDR之P值檢定................................63
圖5.10.1 SFDR之響應期望圖...........................63
圖5.10.2 WCR之響應期望圖............................64
圖5.11 最佳化功率消耗之功率消耗表面回應3D圖.........65
圖5.12 最佳化WCR結果之功率消耗表面回應3D圖..........66
圖5.13 最佳化SFDR之SFDR表面回應3D圖.................67
圖5.14 最佳化WCR之SFDR表面回應3D圖..................68
圖5.15 最佳化ADC之暫態分析 @ fin=1MHz...............69
圖5.16 最佳化ADC之FFT轉換頻譜模擬圖.................69
圖5.17 微分非線性誤差 (DNL) 模擬結果................70
圖5.18 積分非線性誤差 (INL) 模擬結果................70
圖5.19 六位元類比數位轉換器之佈局圖.................71
圖5.20 ADC之Post-Simulation.........................71
圖5.21 ADC之量測示意圖..............................72

表目錄
表3.1 本論文之電壓比較器規格表......................21
表3.2 本論文之數位編碼器規格表......................26
表3.3 六位元類比數位轉換器規格表....................30
表4.1 本論文所挑選的控制因子........................34
表4.2 快閃式類比數位轉換器控制因子之上、下限值......35
表4.3 快閃式類比數位轉換器電路之Box-Behnken 實驗矩陣........39
表5.1 各別最佳化之結果對照表........................53
表5.2 最佳化後六位元類比數位轉換器規格表............73
表5.2.1 使用最佳化之前後性能規格比較表..............74
表5.3 與他篇論文電路效能規格比較....................75

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