本文所完成之FPGA內嵌DSP處理器，只佔用不到Xilinx XC3S500E Spartan-3E FPGA資源的5%，因此藉由於此軟硬體共同設計的數位信號處理器，可具有高面積效率之優勢。此可重組態、可配合應用來進行指令群裁剪工作之ASIP(Application Specific Instruction Set Processor)數位信號處理器，除了適用單通道信號處理外，對於取樣頻率一致的多通道信號處理上，也能夠以分時多工軟體設計法達成多通道信號處理任務；而當多通道信號的取樣頻率不一致時，可以利用多重中斷控制器，處理多重取樣頻率的多通道信號處理問題。也因為高面積效率而可在單一的FPGA上，同時植入數個不同功能的數位濾波器或是DSP函數模組，以增加應用系統的功能效率與設計彈性；當然也可以串接模式，在單一的FPGA上同時植入數個不同功能的FIR數位濾波器，串接組成更多階的數位濾波器；因為串接的FIR數位濾波器是同時執行，可以藉由分散式處理而有效提昇系統速度。

This paper proposes a hardware/software co-design approach to reconfigure a RISC processor which is used to implement a digital filter. According to practical requirement, the application specified instruction set can be tuned, and then the processor hardware can be reconfigured to achieve higher area efficiency. With compact instruction set and single clock execution speed, the FIR design affords high speed performance for both MAC parallel procession and those HDL programs which need sequential procession.
The proposed FIR filter only consumes 5 % of Xilinx XC3S500E Spartan-3E FPGA chip area. With high area efficiency, the digital filter is not only for single channel signal processing, but also for multi-channel signal processings with same sampling frequency, which is designed by time-sharing software engineering. When the sampling frequencies of multi-channel signal are inconsistent, we can build into several different FIRs or DSP modules in a single FPGA to increase the system performance and design flexibility. Further, we can increase FIR tapping number by cascading model, or upgrading FIR sampling speed by parallel model.

中文摘要 -------------------------------------------------------------------- i
英文摘要 -------------------------------------------------------------------- ii
誌謝 -------------------------------------------------------------------- iii
目錄 -------------------------------------------------------------------- v
表目錄 -------------------------------------------------------------------- Vi
圖目錄 -------------------------------------------------------------------- vii
一、 緒論-------------------------------------------------------------- 1
1.1 研究背景-------------------------------------------------------- 1
1.2 研究動機與目的 4
二、 數位濾波器簡介與原理-------------------------------------- 7
2.1.1 數位濾波器簡介----------------------------------------------- 7
2.1.2 半頻帶之低通數位濾波器----------------------------------- 8
2.2.1 FIR 數位濾波器之特性-------------------------------------- 9
2.2.2 FIR數位濾波器原理與處理法------------------------------ 11
三、 ASIP處理器設計---------------------------------------------- 14
3.1 PicoBlaze Microcontroller ----------------------------------- 15
四、 系統設計FIR filter與模擬---------------------------------- 19
4.1 硬體純VHDL設計法---------------------------------------- 20
4.2 軟、硬體共同設計法----------------------------------------- 24
五、 模擬與驗證----------------------------------------------------- 29
5.1 FIR數位濾波器設計------------------------------------------ 29
5.2 以0.3Hz與0.31Hz混波訊號進行濾波------------------- 33
5.21 硬體VHDL設計與模擬------------------------------------- 33
5.22 HW/SW設計與模擬------------------------------------------ 35
5.23 MATLAB模擬與驗證---------------------------------------- 36
5.24 濾波值比較----------------------------------------------------- 37
5.3 以0.3Hz與0.37Hz混波訊號進行濾波------------------- 39
5.31 硬體VHDL設計與模擬------------------------------------- 39
5.32 HW/SW設計與模擬------------------------------------------ 41
5.33 MATLAB模擬與驗證---------------------------------------- 41
5.34 濾波值比較----------------------------------------------------- 42
六、 HW/SW 共同設計與FPGA實作驗證-------------------- 44
七、 系統效能-------------------------------------------------------- 47
八、 結論-------------------------------------------------------------- 48
參考文獻 -------------------------------------------------------------------- 49
附錄一 -------------------------------------------------------------------- 50

[1].Katherine Compton, Scott Hauckacm,(2002) “Reconfigurable Computing: A Survey of Systems and Software”, ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171-210.
[2].R. Tessier and W. Burleson,(2001) “Reconfigurable computing for digital signal processing: A Survey”, Journal of VLSI Signal Processing, Vol 28, No.7-27, pp 7-27, 2001.
[3].Paul Ekas, ” FPGA為傳統DSP應用提供靈活可重配置解決方案”, A Global Sources and UBM joint venture, 2007年9月17日.
[4].Xilinx, (2005) XtremeDSP for Virtex-4 FPGAs User Guide.
[5].F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, (2004) “Custom-Instruction Synthesis for Extensible-Processor Platforms,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 23, pp. 216–228, February 2004.
[6].杜中明, 鄭建剛, 數位訊號處理, 儒林圖書有限公司, 1991, 初版.
[7].林世豐, 陳良基, ”濾波器簡介”, DSP專欄, 2001.
[8].Sanjit k. Mitra, (2001) Digital Signal Processing, second edition. McGraw-Hill Companies.
[9].Xilinx, PicoBlaze 8-bit Embedded Microcontroller User Guide, ug129.
[10].Xilinx, (2003)KCPSM3 8-bit Micro Controller for Spartan-3,Virtex-II and Virtex-II PRO,.
[11].Xilinx,Spartan-3E Starter Kit Board User Guide.