臺灣博碩士論文加值系統

在此論文中，我們使用CIC國家晶片設計中心所提供的TSMC 0.35μm SiGe BiCMOS製程技術來設計並實現一個可行的後級限制放大器電路。而後級限制放大器是光通訊電路接收器的後端，主要設計重點是獲得高的增益與高的動態範圍以及良好的穩定性，此外能具有高靈敏度將前級轉阻放大器所輸出的微小訊號放大至穩定振幅輸出。
在我們設計的限制放大器中，我們以三級來實現此電路，分別為限制放大級、阻隔緩衝級以及正射極耦合邏輯輸出緩衝級。在整個製作的過程，主要是以HPICE這套軟體對電路進行模擬與分析。因此，在供應電壓為5V時，總消耗功率為298mW，電路可使輸出推動50Ω負載達到阻抗匹配之用，而輸出電壓擺幅可達675.2mVp-p以及將電壓訊號達到飽和之最小輸入電壓訊號為3.5mV (即輸入動態範圍3.5mV~300mV為39dB) ；則限制放大整體增益可達55dB、頻寬為289MHz，適合應用於155M/bps光通訊系統上，晶片尺寸為600μm × 600μm。

In this thesis, we use TSMC 0.35μm SiGe BiCMOS technology to design and implement a practical limiting amplifier gain post-amplifier circuit. Limiting amplifier is the back-end component of the optical communication receiver, the main design key for obtains the high gain and the high dynamic-range as well as the good stability. Also with high sensitivity to enlarge the small signal which from front-end transimpedance amplifier to the stabilized amplitude output.
We design the limiting amplifier consists with three stages, they were limiting amplifier, JAM buffer, and PECL output buffer, respectively. In this work, the total consumed power is 289mW as the supply voltage is 5V. In the mean time, the output stage can drive 50Ω loaded resistors, and the smallest input voltage sensitivity is 3.5mV. Limiting amplifier gain could also reach to 55dB and 289MHz bandwwidth, which is well suitable for application in 155M/bps optical communications. Chip size is 600μm × 600μm.

中文摘要................................................i
英文摘要...............................................ii
誌謝..................................................iii
目錄...................................................iv
表目錄.................................................vi
圖目錄................................................vii
第一章 緒論.............................................1
1.1 光通訊系統...................................1
1.2 研究方法.....................................3
1.3 論文架構.....................................5
第二章 限制放大級電路之設計與模擬.......................6
2.1 限制放大級電路架構原理與分析.................6
2.1.1 典型差動放大器型態.......................9
2.1.2差動放大器射極退化電阻...................13
2.2 限制放大級回授補償架構......................14
2.3 阻隔緩衝級電路架構..........................16
2.4 電路模擬結果................................17
2.4.1 限制放大級電路模擬......................17
2.4.2 限制放大級回授補償電路模擬..............21
2.4.3 阻隔緩衝級電路模擬......................24
第三章 輸出緩衝級之設計與模擬..........................27
3.1 輸出緩衝級(Output Buffer)架構分析...........27
3.1.1 ECL邏輯電位.............................27
3.1.2 PECL邏輯電位............................28
3.1.3 CML邏輯電位.............................30
3.2 輸出緩衝級電路分析與模擬....................33
3.3 參考電壓偏壓電路(Bias Circuit)模擬..........35
第四章 限制放大器之完整電路整合與佈局..................37
4.1 整體晶片模擬結果(Whole-chip Simulation )....37
4.2 電路佈局(Layout)............................46
第五章 結論............................................54
參考文獻...............................................55
附錄

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