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研究生:溫武傑
研究生(外文):Wu-Chieh Wen
論文名稱:基底電流最大值偏移量於90nmNMOS元件之探討
論文名稱(外文):Shift of Maximum Substrate Current in 90nm NMOS Device
指導教授:王木俊王木俊引用關係
指導教授(外文):Mu-Chun Wang
學位類別:碩士
校院名稱:明新科技大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:96
語文別:中文
論文頁數:87
中文關鍵詞:熱載子效應奈米製程基底電流製程模擬
外文關鍵詞:Hot carrier effectNano manufacturing procesSubstrate currentManufacturing process simulation
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摘 要

隨著製程技術不斷創新,包括閘極氧化層厚度、晶片尺寸、通道長度…等,都不斷的快速縮小。然而元件的操作電壓降低的速度卻無法跟上,因此,加速載子的電場已經是數倍於長通道元件。因此熱載子效應與短通道效應將變的更嚴重。
改善短通道效應彽摻雜汲極(LDD;Lightly Doped Drain)結構是一中普遍採用的方式可以有效改善因臨界電壓(Threshold Voltage)隨通道縮短而下降(Threshold Voltage Roll-off)與汲極引起位能下降(DILB;Drain Induced Barrier Lowering),所造成元件特性的下降。然而因低摻雜汲極之濃度與佈值能量也可能產生元件缺陷進而影響元件的可靠度(Reliability),因此如何顧及短通道元件缺陷及可靠度將是非常重要的。源/汲極可分為延伸區(Extension S/D)與接觸區(Contact S/D)二部分。早期CMOS製程採用LDD設計,是為了改善元件的熱載子效應。作法是將在MOS通道的兩端,側壁子(spacer)的下方植入較源/汲極濃度低的劑量,以降低電場;但是,先進的CMOS元件製程中,由於操作電壓(Vcc)下降極淺的源/汲極接面已不是可靠性的主要重點,此時元件速度為主要重點,因此增加LDD的植入量,以降低源/汲極間之阻值,實為必要之措施。因此,我們改以源/汲極延伸(SDE;Source/Drain Extension)來稱呼。
由於元件通道長度越來越小,接面濃度高且陡峭,來自汲極端的電壓產生極高的電場將產生能帶間直接穿遂(DBTB;Direct Band to Band Tunneling current),會造成額外的汲極電流。一般所指淺接面(Shallow Junction),即指源/汲極延伸區的接面深度,其縱向深度較源/汲極接觸區為淺,主要是考量短通道效應的控制。接面變淺後,源/汲極阻值將上升,這又違背我們對元件的要求,因此提高摻雜濃度以降低源/汲極阻值亦是淺接面努力之方向。由於此源/汲極延伸可以有效降低可靠度問題中的熱載子效應(HCE;Hot Carrier Effect)。藉由量測聯華電子90nm製程之元件與製程模擬SDE來驗證元件內部電場之大小,是本論文研究的重點。
本論文的目的在於研究90nm SDE NMOSFETs的可靠度(Reliability)分析,現今元件尺寸微縮到奈米等級(L~100nm)後,所具有的垂直與水平高電場效應,將更易造成熱載子的產生與元件閘極氧化層間因缺陷所造成閘極漏電流。尤其當元件進入90nm尺寸時,元件的閘極氧化層物性厚度將趨近於1.6nm,載子將更容易穿透(Tunneling)氧化層,熱載子所造成的閘極漏電流也將日趨明顯。本篇論文將量測聯華電子(UMC)90nm製程下,元件之熱載子效應,設定模形,模擬90nm NMOS元件於不同S/D Extension摻雜濃度下,在不同VD電壓下的電場變化。
本論文共分五章,第一章為簡介。第二章為元件物理。第三章為製程模擬,第四章實驗目的與模擬結果,此章節裡面將會討論ISUB量測與SDE製程模擬的相關性,及相關分析以及如何真實應用於製程改善中。第五章為結論。
Abstract
Along with manufacturing process technique continuously innovative, including the thickness of gate oxidation layer, chip size, channel length, etc., all unceasingly downsize fast. However, the decrease of the operation voltage of the device is unable to keep up with it. Therefore, the electric field of acceleration carrier at short-channel site is already several times of that at long channel device. So, the hot carrier effect and the short channel effect will be more serious.
Improving the short channel effect, the structure of lightly doped drain (LDD) is a good way of general adoption which can be effectively improved because of the threshold voltage roll-off and the drain Induced barrier lowering (DILB), causing the drop of device characteristics.
However LDD doping concentration and implemented distribution energy may also generate the device drawback and then influence the reliability of device. How to take channel device defect and reliability into account is very important. Source/Drain (S/D) pole location can be basically divided into two parts, extension S/D and contact S/D. The CMOS manufacturing process adopting LDD design in early days was for improving the hot carrier effect of device. The method is at both ends in MOS channel, implementing into a lower quantity of the source /drain concentration below spacer, in order to reduce the electric field. But in the advanced manufacturing process of CMOS device, due to the descend of the supply voltage (Vcc), the very shallow junction of the source/drain is no longer the main point of the reliability. The speed of the device is impressively focused focal in this moment. Thus, increasing the implementation amount of LDD, and reducing the resistance of source/drain, are the essential methodology in fact. This is why people change that with the source / drain extension (SDE).
Because the channel length of device is smaller and smaller, the junction concentration profile is high and steep. Coming from drain voltage to generate very high electric field causing the direct band to band tunneling current (DBTB) can result in extra S/D current. Generally the shallow junction, points out the entire junction depth of source/drain.
After the junction becoming shallow, the resistance of source/drain will raise and this effect disobeys our request to high-speed device again. Exalt the doping concentration and descending the resistances of source/drain at shallow-junction technique are also a tough task. Because this source/drain extension can effectively reduce the reliability problem of the hot carrier effect (HCE), by measuring the device with UMC 90 nm manufacturing process and assisting the process simulation with ISE software, to verify the intensity of internal electric fields of the device, are the chief targets of this thesis research.
The purpose of this thesis lies in studying the reliability analysis of 90 nm SDE NMOSFETs. At present the device size is tiny to the nanometer grade (L<100 nm). The vertical and horizontal high electric field in operation will make it easier to cause the generation of hot carrier and result in gate oxide leakage.
Particularly, when the device gets into a 90 nm size or below, the thickness of gate oxide will physically tend near 1.6 nm, the moving carriers can more easily tunneling oxide layer. The tunnel phenomenon of gate oxide stressed by hot carrier degradation will be gradually obvious. This thesis measured the hot carrier effect of device under UMC 90 nm manufacturing process and set up some modes to fit the simulation of 90 nm NMOS device mold, 90 nm NMOS under different S/D Extension doping concentrations. The electric field at SDE would change under the different VD voltages.
This thesis is totally divided into 5 chapters; chapter 1 is a brief introduction. Chapter 2 is device physics. Chapter 3 simulates for the manufacturing process, chapter 4 describes experimental purposes and simulating results. Chapter 4 will also discuss the relationship of ISUB measurement, SDE manufacturing process simulation plus related analysis, and how to truly apply on the improvement of the manufacturing process. Chapter 5 is a summary.
目 錄
中文摘要 i
英文摘要 iii
誌謝 vi
目錄 vii
表目錄 ix
圖目錄 x
第一章 緒論 1
1-1 背景 1
1-2 動機 1
1-3 量測方法 2
1-3-1 ID-VGS特性曲線 2
1-3-2 汲極雪崩式熱載子效應(DAHC) 2
1-3-3 通道熱載子效應(Channel Hot Carrier) 2
1-4 論文架構 5
第二章 元件物理 6
2-1 金氧半場效電晶體短通道效應 6
2-2 氧化層缺陷 8
2-2-1 捕陷電荷種類 8
2-2-2 捕陷電荷對元件造成的影響 12
2-3 超薄絕緣層的漏電流傳導機制 14
2-3-1 Direct tunneling 理論 18
2-3-2 F-N tunneling 理論 20
2-3-3 P-F 效應理論 21
2-4 MOS C-V量測原理 23
第三章 元件製程模擬與熱載子分析 27
3-1 製程模擬軟體(ISE-TACD)之簡介 27
3-1-1 擴散模型 27
3-1-2 離子佈植模型 28
3-1-3 氧化模型 30
3-2元件電性模擬軟體(ISE-TCAD)之簡介 31
3-2-1 電流電壓模型 32
3-2-2 遷移率模型 33
3-2-3 邊界條件 36
3-2-4 數值方法 37
3-3 元件縮小與熱載子效應的關係 38
3-3-1 熱載子效應的產生 39
3-3-2熱載子所引起的基底電 40
3-3-3熱載子的元件退化模型 44
3-4 熱載子對元件性能的損害 43
3-4-1解決熱電子效應的方法 43
第四章 實驗目的與模擬結果 46
4-1 整體實驗架構說 46
4-1-1 手動探針量測平台(Manual Probe Station) 46
4-1-2 半導體參數分析儀(Agilent 4156C)47
4-1-3 被動元件精密型RLC表(Agilent 4284A)49
4-2 基底電流量測 50
4-3 量測結果 52
4-4 模擬結果 54
第五章 結論 60
5-1 討論 60
5-2 未來展望 60
參考文獻 62
參考資料
[1]原著/James D. Plummer, Michael D. Deal, Peter B. Griffin, 譯者/羅正忠,李平,鄭湘原,〝半導體工程─先進製程與模擬〞,初版二刷,p.1~3,2005
[2]S. M. Sze, “Physics of Semiconductor Devices,”, p.469~486 Second printing July 1985
[3]ITRS, http://public.itrs.net
[4]S. Tam, P. K. Ko, and C. Hu, “Lucky-Electron Model of Channel Hot-Electron Injection in MOSFET’s,” IEEE Transaction on Electron Devices, Vol.31, p.1116. September 1984.
[5]作者:Donald A. Neamen, 譯者:李世鴻,陳勝利,〝半導體物理元件〞,Second Edition, p.539, 2003
[6]作者:Donald A. Neamen, 譯者:李世鴻,陳勝利,〝半導體物理元件〞,Second Edition, p.469~471, 2003
[7]Chang-Hoon Choi, Kwang-Hoon Oh, Jung-Suk Goo, Zhiping Yu, and Robert W. Dutton, “Direct Tunneling Current Model for Circuit Simulation, ”International Electron Devices Meeting, P.735 – 738, 1999
[8]Yuan Taur, Tak H. Ning, “Fundamentals of Modern VLSI Devices,”p.96, 2000
[9]R.M.Wallace and G. Wilk, “High-k Dielectric Materials for Microelectronics,” Critical Reviews in Solid State and Materials Sciences 28, 231, 2003
[10]Yuan Taur, Tak H. Ning,“Fundamentals of Modern VLSI Devices,”p.82, 2000
[11]施敏原著,張俊彥譯著,〝半導體元件物理與製作技術〞,中華民國90年7月10日三版四刷
[12]原著/James D. Plummer, Michael D. Deal, Peter B. Griffin, 譯者/羅正忠,李嘉平,鄭湘原,〝半導體工程─先進製程與模擬〞,第四章,p.151~193, 2005
[13]王雲珍著,〝半導體〞,民國81年(1992)
[14]Yuan Taur, Tak H. Ning, “Fundamentals of Modern VLSI Devices,”p.86~90, 2000
[15]作者:Donald A. Neamen, 譯者:李世鴻,陳勝利,〝半導體物理元件〞,Second Edition, p.484, 2003
[16]Mauro Zambuto, “Semiconductor Devices,”McGraw-Hill Book Company, Ch. 9, p.284~332, 1989
[17]Dieter K. Schroder, “Semiconductor Material and Device Characterization,”Third Edition, p.339~347, 2006
[18]Yuan Taur, Tak H. Ning, “Fundamentals of Modern VLSI Devices,”p.94~95, 2000
[19]Edward S. Yang,“Fundamentals of Semiconductor Devices,”Ch. 2, p.32~46, 1978
[20]賴俊羲,〝以多靶式射頻磁控濺鍍系統沉積高介電常數之鈦酸鍶鋇薄膜之研究〞,私利中原大學電子工程學系碩士論文, p.46, 民國八十七年
[21]李雅明,〝固態電子學〞, p.415~416, 民國八十四年
[22]Yuan Taur, Tak H. Ning, “Fundamentals of Modern VLSI Devices,” p.96~97, 2000
[23]Chang-Hoon Choi, Kwang-Hoon Oh, Jung-Suk Goo, Zhiping Yu, and Robert W. Dutton,“Direct Tunneling Current Model for Circuit Simulation,” International Electron Devices Meeting, P.735 – 738, 1999
[24]Yuan Taur, Tak H. Ning,“Fundamentals of Modern VLSI Devices,”p.96, 2000
[25]Dieter K. Schroder,“Semiconductor Material and Device Characterization,”Third Edition, p.390, 2006
[26]S. Croci, J. P. Sorbier, C. Plossu, “Stress Induced Leakage Current under EEPROM like Dynamic Stress.”
[27]李雅明,〝固態電子學〞,p.440,民國八十四年
[28]Yuan Taur, Tak H. Ning,“Fundamentals of Modern VLSI Devices,”p.71, 2000
[29]Dieter K. Schroder, “Semiconductor Material and Device Characterization,”Third Edition, Ch. 6, p.337~419, 2006
[30]莊達人編著,〝VLSI 製造技術〞,中華民國89年12月10日四版八刷,p.548~549
[31]TSUPREM-4 Manual, Technology Modeling Associates, Inc., Palo Alto, CA,USA, 1995.
[32]Donald A. Neamen, Semiconductor Physics & Devices : Basic Principles, 2nd ed., Richard D. Irwin, USA, 1997
[33]MEDICI Manual, Technology Modeling Associates, Inc., Palo Alto, CA, USA, 1996.
[34]Watt, J. T.,”Surface Mobility Modeling,” presented at Computer-Aided Design of IC Fabrication Processes, Stanford University, Aug 3, 1988.
[35]Caughey, D. M. and Thomas, R. E., “Carrier mobilities in silicon empirically related to doping and field,” Proceedings of the IEEE, vol. 55, iss. 12, P.2192 - 2193 Dec. 1967
[36]Christopher F. Codella and Seiki Ogura, “Halo Doping Effects in Submicron DI-LDD Device Design,” IEDM Tech. Dig., pp 230-233 1985.
[37]Hiroaki Mikoshiba, Tadahiko Horiuchi, and Kuniyuki Hamano, “Comparison of Drain Structures in n-ChannelMOSFET’s,” IEEE TRANS ON ELECTRON DEVICES, VOL. ED-33, NO. 1, JANUARY 1986
[38]Jan M.Rabaey, Anantha Chandrakasan, Borivoje,〝數字集成電路——設計透視(第二版)〞,美國,清華大學出版社,P.115,2004.3
[39]StanleyWolf, Tauber R N, “Silicon Processing for the VLSI Era-Volume3:The Submicron MOSFET,” California, Lattice Press, 1994.
[40]ISE-TCAD Release 10.0 manual.
[41]P. Aminzadeh, M. Alavi, D. Scharfetter, “Temperature dependence of substratecurrent and hot carrier-induced degradation at low drain bias,” Tech. Dig. of VLSI Symp., pp. 178~179, 1998.
[42]B. Eitan, et al, “Impact ionization at very low voltages in silicon,” J. Appl. Phys., Vol.53, No.2, pp.1244~1247, 1982.
[43]J.H. Huang, et al., “Temperature dependence of MOSFET substrate current,” IEEE Electron Device Lett., vol. 14, iss. 5, pp.268~271, May 1993
[44]M. H. DeGroot, “Probability and Statistics,” Reading, Massachusetts: Addison-Wesley, 2nd ed., 1989.
[45]Ootsuka, F.,”The evaluation of the activation energy of interface state generation by hot-electron injection,” IEEE TRANS. Vol.38. iss.6, p.1477-1483, June 1991
[46]Chang-Hoon Choi, Jung-Suk Goo, Zhiping Yu, and Robert W. Dutton, “Shallow Source/Drain Extension Effects on External Resistance in Sub-0.1 m MOSFET’s,” IEEE TRANS. on ED., vol. 47, no. 3, March 2000
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