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研究生:石逸群
研究生(外文):Yi-Chun Shih
論文名稱:金氧半電容元件中硼穿透與閘極空乏效應之研究
論文名稱(外文):Effects of Boron Penetration and Poly Gate Depletion on Characteristics of Metal-Oxide-Semiconductor Capacitors
指導教授:武東星
指導教授(外文):Dong-Sing Wuu
學位類別:碩士
校院名稱:國立中興大學
系所名稱:材料科學與工程學系
學門:工程學門
學類:綜合工程學類
論文種類:學術論文
畢業學年度:96
語文別:中文
論文頁數:76
中文關鍵詞:P 通道金屬氧化物半導體電容元件N通道金屬氧化物半導體電容元件去耦合電漿氮化閘極保護層硼穿透閘極空乏
外文關鍵詞:P-type channel metal-oxide-semiconductor capacitor (PMOS)N-type channel metal-oxide-semiconductor capacitor (NMOS)Decoupled plasma nitridation (DPN)Gate barrier oxideBoron penetrationPoly depletion
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本論文主要探討在P 通道金屬氧化物半導體電容元件(p-type channel metal-oxide-semiconductor capacitor: PMOS capacitor)中使用N 型複晶矽( N+ poly gate ) 與P 型複晶矽( P+ poly gate) 結構與特性的差異,同時針對P 通道金氧半電容元件使用N+ poly gate 結構的埋藏通道與P+ poly gate 結構的表面通道分別作討論,我們發現在使用P+ poly gate 結構的表面通道時,可以利用去耦合電漿氮化(decoupled-plasma-nitridation: DPN)與閘極保護層等製程來減少硼穿透與閘極空乏的現象。
在N 通道金屬氧化物半導體電容元件(n-type channel metal-oxide-semiconductor capacitor: NMOS capacitor) 中,若使用N+ poly gate 結構結合去耦合電漿氮化製程可減少硼離子擴散所造成的臨界電壓偏移,使得N 通道金氧半電容元件的臨界電壓降低,我們針對N+ poly gate 結構的閘極濃度與閘極空乏作研究,並可得出NMOS電容元件的最佳條件。
在P 通道金屬氧化物半導體電容元件使用N+ poly gate 的結構中,當透過植入反轉為P+ poly gate 的摻雜時,我們詳細討論了遭反轉後的表面通道特性,並且利用DPN 製程與閘極保護層製程克服硼穿透與擴散產生的閘極空乏,如此可以平衡硼穿透與閘極空乏效應並減少臨界電壓偏移。
從本論文的研究中可發現當N 型複晶矽閘極使用磷的臨場( in-situ )濃度為2.0×1020 cm-3 ,並且透過P 型閘極摻雜製程,可以使得反轉為P 型複晶矽閘極,而使用DPN 與閘極保護層製程將可使得NMOS電容元件的閘極空乏率低於10% 並減少臨界電壓偏移,而使用DPN 與閘極保護層製程於PMOS電容元件,其中閘極空乏率為27%而且並無硼穿透效應。

關鍵詞: P 通道金屬氧化物半導體電容元件;N通道金屬氧化物半導體電容元件;去耦合電漿氮化;閘極保護層;硼穿透;閘極空乏
This thesis describes the characterization and performance difference of N+ and P+ poly gates in the p-type channel metal-oxide-semiconductor (PMOS) capacitors. A major discussion of this study focuses on the N+ poly gate buried channel and the surface channel in the PMOS capacitors. We also try to reduce the boron penetration and poly depletion by adopting a decoupled-plasma-nitridation (DPN) process and a gate barrier oxide on the P+ poly gate surface channel.
The N+ poly gate combining with the DPN process in n-type channel metal-oxide-semiconductor capacitor can enable the reduction of the threshold voltage shift caused by boron out diffusion. Moreover, it can reduce the threshold voltage shift in n-type channel metal-oxide-semiconductor (NMOS) capacitor. Thus one can probe the optimum process parameters via the dosage of N+ poly gate and poly depletion conditions.
In this thesis, the features of surface channels after inversion is discussed when the PMOS capacitor adopts N+ poly gate to embed inversion as the P+ poly gate dopant. As a result, one can use the DPN process and the gate barrier oxide to overcome either boron penetration or poly depletion caused by the boron ion diffusion and to balance the boron penetration and the poly depletion effect. Furthermore, this can also reduce the threshold voltage shift.
Finally, for the N+ poly gate adopting in-situ phosphorous dosage of 2.0×1020 cm-3 and enabling the P+ poly gate dopant inversion occur through the P+ pate dopant, the poly depletion rate will be lowered than 10% by using both the DPN process and gate barrier oxide. Besides, it can reduce the threshold voltage shift and leads the poly depletion rate to 27% without the boron penetration effect by adopting the DPN process and the gate barrier oxide in PMOS capacitors.

Keywords: P-type channel metal-oxide-semiconductor capacitor (PMOS)
N-type channel metal-oxide-semiconductor capacitor (NMOS) Decoupled plasma nitridation (DPN)
Gate barrier oxide
Boron penetration
Poly depletion
書名頁
審核頁
誌謝-------------------------------------------------------i
中文摘要-------------------------------------------------iii
英文摘要---------------------------------------------------v
目錄-----------------------------------------------------vii
表目錄----------------------------------------------------ix
圖目錄-----------------------------------------------------x
第一章 緒論------------------------------------------------1
1.1 背景-----------------------------------------------1
1.2 量測方法-------------------------------------------5
1.2.1 閘極氧化層C-V 曲線---------------------------5
1.2.2 閘極氧化層崩潰電壓---------------------------5
1.2.3 閘極氧化層漏電流-----------------------------6
1.3 論文架構-------------------------------------------7
第二章 去耦合電漿氮化中不同氮濃度之比較-------------------11
2.1 去耦合電漿氮化製程步驟----------------------------11
2.2 DPN製程中氮濃度之實驗步驟-------------------------13
2.3 DPN製程中氮濃度之結果與討論-----------------------15
第三章 DPN 運用於N 型複晶矽閘極---------------------------23
3.1 DPN 製程與元件特性--------------------------------23
3.2 DPN 製程運用於元件之實驗步驟----------------------23
3.3 DPN 製程運用於元件之結果與討論--------------------25
第四章 P 型複晶矽閘極與閘極保護層之現象-------------------43
4.1 使用P 型複晶矽閘極之特性--------------------------43
4.2 使用P 型複晶矽閘極之實驗步驟----------------------43
4.3 使用P 型複晶矽閘極之結果與討論--------------------46
第五章 調變N 型複晶矽閘極濃度與P+ poly IMP 反轉濃度並改變閘極氧化層之現象--------------------------------------------56
5.1 調變閘極濃度與氧化層厚度之特性--------------------56
5.2 調變閘極濃度與氧化層厚度之實驗步驟----------------56
5.3 調變閘極濃度與氧化層厚度之結果與討論--------------59
第六章 結論與未來展望-------------------------------------68
參考文獻--------------------------------------------------70
作者簡介--------------------------------------------------76
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