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研究生:張峻宇
研究生(外文):Chun-Yu Chang
論文名稱:非同步反饋架構下光封包交換器的排程方法與效能研究
論文名稱(外文):Performance Analysis of Delay-line Buffer Management for Feedback Asynchronous Optical Packet Switches
指導教授:林偉林偉引用關係
學位類別:碩士
校院名稱:國立中興大學
系所名稱:資訊科學與工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:96
語文別:中文
論文頁數:37
中文關鍵詞:光交換器FDL緩衝排程演算法
外文關鍵詞:Optical packet switchfiber delay linebuffer scheduling
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網路發展迅速,人們對網路的需求越來越大,為了達到更快的傳輸速度,提升交換器的效能是必要的,而交換器的一項重要工作就是解決封包在交換器內的碰撞問題(Contention problem),碰撞問題會造成網路的擁塞或是封包的遺失,導致整體網路的慢速,因此解決與減少封包在交換器上的碰撞一直是網路傳輸上一個重要的課題。
所謂封包發生碰撞是指多於一個封包要同時通往同一輸出埠(Output port),交換器無法同時傳送這些封包到輸出埠,所以必須丟棄某些封包。在電子式的領域中,可以將會發生碰撞的封包轉換成電的形式儲存在記憶體內做緩衝,待不會發生碰撞時,再將其轉換回光的形式送出,這種光電的轉換(O/E/O)除了需要耗費成本以外,速度也受限於記憶體的存取速度。但是在光領域中,考慮全程以光型態傳送,現今並沒有記憶體的可以用來儲存光型態的封包,取而代之使用的是Fiber-delay-lines( FDLs),FDL同樣可以緩衝封包一段時間來達到解決碰撞的目的。在行進FDL的過程即是緩衝,過程中並不需要光電轉換,除了較節省成本之外,提升傳送速度。未來網路的傳輸朝往全程光型態傳送以彌補現階段要轉換成電子型態的缺點。
在有限的波長使用限制之下,相較於波長轉換(Wavelength Conversion),使用FDL的效能來得更好且更有彈性。因為使用FDL較彈性相對也比較複雜,排程的工作就顯得相當重要,好的排程演算法可以降低封包的遺失率以及封包的延遲時間。本論文中,我們在Feedback架構下提出三種排程演算法,分別為Available Unused Delay-Line scheme (AUDL),Available UnScheduled Delay-Line scheme (AUSDL) and Available UnScheduled Delay-Line with Group selection (AUSDL-G)。依據模擬的結果AUDL可以有效的使用FDL資源並達到很好的效能,但是它的複雜度很高,在實行上有其困難度。為了減少複雜度,我們相繼提出AUSDL以及AUSDL-G排程演算法,依據我們模擬的結果,具有較低複雜度的排程演算法AUSDL以及AUSDL-G在某些情況之下可以達到與AUDL相近的效能。而FDL的數量與允許繞圈數是硬體實做上的設定,我們著重於此兩個數據的觀察,評估其對效能的影響力,以幫助實際設計上成本的考量。
The demand for higher communication bandwidth has been growing at a rapid pace led by diverse network services. It is necessary to improve the node throughput to achieve high-speed data transmission. Wavelength Division Multiplexing (WDM) is a promising approach that can provide an aggregate throughput of the order of terabits per seconds. It is widely favored as a practical solution to fulfill the growing communication demand. For enhancing the transmission rate from electronic domain, the future WDM systems are likely to be implemented by all-optical components.
Packet contention resolution is a major issue in optical packet switching networks, especially in asynchronous switching networks. In asynchronous switches, packets arrive in continuous-time fashion, and there may be more than one packet destined to the same output port simultaneously. In the electronic domain, this problem is typically solved by buffering the contending packets. However, RAM-like buffering is not yet available in the optical domain. In optical networks, fiber-delay-lines (FDLs) are used to delay packets for a fixed amount of time. Different from Wavelength Conversion technology, fiber delay line provides flexible buffering strategies, especially when the number of wavelengths is limited.
A limitation of optical buffering is that FDLs may be bulky, since the length of a fiber is directly proportional to the travailing time of light in the fiber. Efficient buffer architecture and management play an important role in reducing packet blocking probability and the number of buffers. In the thesis, we investigate three buffer management schemes for feedback-type optical packet switches: they are Available Unused Delay-Line scheme (AUDL), Available UnScheduled Delay-Line scheme (AUSDL) and Available UnScheduled Delay-Line with Group selection (AUSDL-G). The simulation results show that AUDL scheme yields the highest utilization rate of FDL. However, the complexity for implementing the AUDL scheme is considerably high and may become infeasible in practice. To reduce the complexity of the AUDL scheme, we further propose AUSDL and AUSDL-G schemes. Based on the simulation results, we find that the AUSDL and AUSDL-G schemes perform as well as the AUDL scheme in terms of packet blocking probability, but with much lower computation complexity.
誌謝 i
摘要 ii
Abstract iii
目錄 iv
表目錄 v
圖目錄 vi
第一章 簡介 1
1.1 論文簡介 1
1.2 論文架構 2
第二章 背景知識及相關研究 3
2.1 封包交換器 3
2.2 光交換器(Optical Packet Switch) 3
2.3 交換器架構 5
2.3.1 輸入端佇列交換器(Input Queue Switch) 5
2.3.2 輸出端佇列交換器(Output Queue Switch) 6
2.3.3 Feed-forward架構 7
2.3.4 Feedback架構 8
2.4 相關研究 10
第三章 研究主題 11
3.1 使用的Feedback封包交換器架構與FDL分布 11
3.2 排程演算法 13
3.2.1 AUDL演算法 15
3.2.2 AUSDL演算法 18
3.2.3 AUSDL-G演算法 20
第四章 效能評估 23
4.1 模擬環境介紹及參數設定 23
4.2 模擬結果 24
4.2.1 Output-based架構模擬結果 24
4.2.2 Share-based架構模擬結果 32
第五章 結論 35
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