臺灣博碩士論文加值系統

本論文主要運用變壓器電壓控制振盪電路架構，理論推導和實際驗證變壓器之不同圈數比(如N)和非理想耦合效應(如K)對電壓控制振盪電路之關係。首先，介紹振盪器基本原理和各種不同結構的變壓器振盪電路，比較各種變壓器振盪電路之優缺點，說明本論文中建議之變壓器振盪電路[16]有較佳的低電壓及低相位雜訊優點，而且線路架構較簡單。
傳統LC振盪電路影響相位雜訊大小主要在電感元件Q值，對於變壓器振盪電路因電感耦合及CMOS的 效應故無法直接引用，必須利用電路 值來分析，故先計算變壓器振盪電路輸出對輸出之轉換函數，然後可得電路輸出阻抗後再運用公式[23][24][25]推導出電路 值，由此理論可證明變壓器振盪電路有較佳 值特性，故相位雜訊亦相對較佳，但在許多變壓器振盪電路參考文獻[15][16][17][18][19]中卻假設變壓器參數K=1，且對於最佳N值無法提出理論或實際關係證明，因此本論文依據實際變壓器N值及K值特性再深入推導N及K與頻率及相位雜訊關係，根據推導結果得知，當K值增加時會降低相位雜訊，但最佳N值點因影響變數太多，故不容易利用公式推導演算，這是從理論方面驗證。
其次，在實際模擬方面，利用ADS模擬各種不同平面型結構之變壓器元件對N值及K值關係，並歸納出提升平面型變壓器N值及K值方法，然後選用數組不同K值變壓器，將初次級圈數比依序紀錄每個不同K值與N值之變壓器的S參數，再將這些所有的S參數代入振盪電路中模擬並記錄結果，從模擬結果得知，最佳相位雜訊值之點是與電路 值有關，而電路 值又決定於 值，即變壓器 值最大時有最佳相位雜訊值。另K值選用較大者亦可降低相位雜訊，但須特別注意的是，N值必須選擇靠近 值最大處，否則K值選用較大者其相位雜訊反而較差，所以根據選用之變壓器特性，我們提出N值必須大於2以上及K值需大於0.7，如此才可設計出較佳特性之變壓器振盪電路。另外在工作頻率方面，當N值或K值增加時，工作頻率會降低。
最後，針對射頻2.4GHz頻段利用TSMC 0.18um CMOS技術製作兩個變壓器電壓控制振盪電路，量測此兩個變壓器電壓控制振盪電路之工作頻率及相位雜訊值，從量測數據得知無論是公式推導或是實際模擬方面，都證明以上分析結果是一致的。

This research is focus on the formula derivation of the transformer with different turn ratio (i.e., N) and non-ideal coupling coefficient (i.e., K) by using a circuit platform – voltage control oscillator (VCO). Firstly, the fundamental theory of oscillators and transformer-based VCO’s circuit are addressed comprehensively.
Generally, the phase noise is influenced by the inductor’s Q value in traditional LC VCO. Since the coupling coefficient and transductance of CMOS are included in circuit, the transformer applied to the VCO is analyzed by using the value. After a lengthy derivation, the result exhibits high value causing to low phase noise. In reported literature [15][16][17][18][19], most transformer-based VCOs assume the K equals 1 and don’t define the N value. In this work, the relationship of oscillator frequency and phase noise with N and K values of actual transformer is studied. The derived formula discloses that the phase noise decreases during the K value increased. Therefore, the optimum point of N value is difficult to calculate by one formula.
Secondly, the Agilent ADS software is used to simulate different construction of transformer, afterward the relationship of N and K value in different transformer layout is acquired. Hence, the transformer-based VCO is simulated using the record data. The optimum point of phase noise is corresponding to the highest value in circuit simulation. Moreover, the high K value results in low phase noise. Notably, the selection of N value approaches the maximum value which can achieve low phase noise. Otherwise, the phase noise will increase by higher K value. Accordingly, the thesis specifies the N value must greater than 2 and the K value greater than 0.7. On this selection, the working frequency will decrease during the increased N or K value.
Lastly, the TSMC 0.18um CMOS technology is implemented to fabricate 2 transformer’s VCO circuits. Both frequency and phase noise are measured on wafer. The measurement results demonstrate the correction of formula derivation in this thesis.

致謝詞 i
中文摘要 ii
英文摘要 iii
目錄 iv
表目錄 vii
圖目錄 viii
第一章 緒論
1.1 研究動機 1
1.2 文獻回顧 2
1.3 論文架構 3
第二章 電壓控制振盪器
2.1 電壓控制振盪器原理 5
2.1.1 雙端負迴授系統 6
2.1.2 單端能量補償系統 8
2.2 LC壓控振盪器 11
2.2.1 壓控振盪器的數學模型 12
2.2.2 LC壓控振盪器的限制 13
2.3 變壓器壓控振盪器 15
2.3.1 變壓器壓控振盪器原理分析 17
2.4 結論 19
第三章 可變電容器
3.1 可變電容器分類 20
3.2 PN介面可變電容器 20
3.3 MOS可變電容器 20
3.4 逆向MOS可變電容器 22
3.5 累積型MOS可變電容器 23
3.6 可變電容器之模擬 24
3.7 結論 24
第四章 變壓器
4.1 變壓器之自感與互感 25
4.2 變壓器之互感關係 28
4.3 變壓器模型 28
4.4 變壓器模擬 29
4.5 結論 32
第五章 相位雜訊分析
5.1 相位雜訊的定義 33
5.2 線性時變分析 36
5.2.1 雜訊對相位的影響 36
5.2.2 相位對電壓的轉換 39
5.2.3 相位雜訊功率 40
5.3 結論 42
第六章 變壓器振盪電路最佳化
6.1 低功率消耗設計 43
6.2 變壓器振盪電路頻率分析 44
6.3 變壓器振盪電路相位雜訊分析 48
6.3.1 元件Q值 49
6.3.2 電路負載Q值 50
6.4 變壓器振盪電路N值與相位雜訊分析 51
6.5 變壓器振盪電路K值與相位雜訊分析 53
6.6 結論 53
第七章 模擬與量測
7.1 振盪電路設計 56
7.2 變壓器設計 57
7.3 測試考量及IC Layout 58
7.4 測試及模擬 60
7.5 結論 63
第八章 總結和未來發展
8.1 總結 65
8.2 未來發展 66
附錄
A 公式驗證推導 67
B 變壓器振盪電路 及 推導 68
C 變壓器振盪電路N值與 推導 71
參考文獻 74

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