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研究生:林心蕾
研究生(外文):Hsin-Lei Lin
論文名稱:應用於多輸入多輸出-正交分頻多工無線通訊系統之同步及解碼電路之設計
論文名稱(外文):Design of Synchronization and Decoder Circuits for MIMO-OFDM Wireless Communication Systems
指導教授:張振豪
學位類別:博士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:100
中文關鍵詞:多輸入多輸出同步電路多輸入多輸出解碼電路調節旋轉數位計算球型解碼器
外文關鍵詞:MIMOSynchronizationMIMO decoderCORDICSphere decoder
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基於現今無線通訊系統利用正交分頻多工及多輸入多輸出的技術,提高無線傳輸通道效能及資料傳輸速度,故本論文針對以IEEE 802.11n為基礎架構的無線通訊網路系統接收端,分別提出同步電路與多輸入多輸出解碼電路相關研究設計。
頻率的飄移在正交分頻多工技術上的影響較為敏感,因而更突顯接收端同步電路對於無線區域網路的重要性。在此,我們亦配合多輸入多輸出無線通訊系統,結合「調節旋轉數位計算」旋轉演算法和三角函數,提出一個用於同步電路的數位震盪器。此論文之同步電路以二乘二的傳輸天線系統為設計,利用TSMC 0.18 μm 1P6M CMOS製程模擬邏輯電路,相較於以傳統記憶體為基礎的設計方式下,可以達到使用少量記憶體之目的;相對於「調節旋轉數位計算」架構下,可以減少其曡代程序。
同時研發「結合V-BLAST 及部分球型解碼器」演算法,用以解碼在多輸入多輸出系統上的空間分割多工技術,並設計有效率的候選人搜尋機制,來提高電路實現的高資料流及降低硬體實現之成本。多輸入多輸出解碼器的設計則推進為較複雜的四乘四多輸入多輸出的無線傳輸系統,如此在TSMC 90nm製程下,可達到以166 兆赫為時脈操作頻率之每秒傳輸95MB高速傳輸系統目的。
The designs of synchronization and MIMO decoder are proposed in this dissertation since the MIMO method and OFDM technique can be used for improving either the performance or the data rate of wireless communication.
The synchronization is investigated since the frequency is more sensitive in OFDM system. A novel digital oscillator of synchronization combined with the CORDIC algorithm and Sinusoidal function is designed for the MIMO wireless communication. The synchronization was implemented using TSMC 0.18 μm 1P6M CMOS technology at 1.8V, and the core area was about 1.682 mm^2 of a 2-by-2 antenna system. A memory-based oscillator needs an accumulator and a sin/cos generator to perform frequency compensation, and the size of memory severely limits the precision. The proposed circuit reduces the memory by using sinusoidal. Furthermore, comparing to the iterative CORDIC computation, the proposed CSIO architecture operates the CORDIC only once.
Moreover, a high throughput and low-cost JVBPSD algorithm using efficient candidate searching is proposed for SDM-MIMO wireless system. It can operate at a 166 MHz clock frequency, and the average throughput of the efficient candidate searching MIMO decoder is 95 Mbps with 64-QAM modulation at 30 dB SNR. The core area of the proposed MIMO decoder using a TSMC 90nm technology with different modulations in a 4-by-4 SDM-MIMO wireless system is about 0.675 mm^2.
Chapter 1
Introduction 1
1.1 Background 1
1.2 Motivations 3
1.2.1 The Design of the MIMO-OFDM Wireless Communication System 3
1.2.2 Synchronization of MIMO-OFDM wireless system 4
1.2.3 FFT 4
1.2.4 The MIMO Decoder Combined with V-BLAST and SDM Method 5
1.3 Contributions of the Dissertation 6
1.4 Organization of the Dissertation 7
Chapter 2
The MIMO-OFDM System 9
2.1 The parameters of the MIMO-OFDM system 9
2.2 The Transmitted signal 15
2.3 Channel Model 23
Chapter 3
The Receiver of MIMO-OFDM System 27
3.1 The Algorithm of the MIMO Synchronization 27
3.1.1 The Timing Synchronization of the MIMO Synchronization 27
3.1.2 The Frequency Synchronization of the MIMO Synchronization 28
3.1.3 The Phase Tracking of the MIMO Synchronization 31
3.2 The MIMO-OFDM System with 64/128-FFT 32
3.3 The MIMO Decoder 34
3.3.1 The Algorithm of the STBC Scheme of MIMO Systems 36
3.3.2 The Algorithm of the SDM Method 38
3.3.2.1 The V-BLAST Algorithm 39
3.3.2.2 The Sphere Decoding Algorithm 40
3.3.3 The Proposed MIMO Detector Method 41
3.3.3.1 Radius Constraint of the Sphere 42
3.3.3.2 One Straight Branch of the Tree 43
3.3.3.3 QR-Decomposition 43
3.3.3.4 Slicer 44
3.3.3.5 SCD 45
3.3.3.6 Tree Pruning 45
3.3.3.7 Min-search of Euclidean Distance 46
3.4 Simulation of the MIMO-OFDM Wireless Communication System 47
3.4.1 The Simulation Results of the MIMO Synchronization 47
3.4.2 The Simulation of the Proposed MIMO Detector Method 50
Chapter 4
The Architecture of the MIMO-Synchronization 59
4.1 The Architecture of the 2×2 MIMO Synchronization with CSIO 61
4.1.1 The Cross-correlation for Timing Synchronization 61
4.1.2 The Auto-correlation for Timing Synchronization 62
4.1.3 The Modified Frequency Synchronization 63
4.1.3.1 The CORDIC Architecture 64
4.1.3.2 The Modified Oscillator Architecture 66
4.1.4 Re-modified Booth Multiplier 70
4.2 Implementation and Comparison Results 72
Chapter 5
The Architecture of the MIMO Decoder 76
5.1 The Space-Division Multiplexing Method 76
5.2 The Proposed Architecture of SDM-MIMO Decoder 80
5.2.1 The Pre-processor with QR-decomposition 80
5.2.2 Proposed Efficient Candidate Searching 81
5.2.2.1 Definition of the radius for candidate searching 81
5.2.2.2 Proposed Searching by Constellation-Shifting with Scalable Radius 82
5.2.2.3 Successive Cancellation Detection (SCD) 86
5.2.3 Bubble Sorting for the Minimum Euclidean Distance 87
5.3 RTL simulation and Implementation Results 88
Chapter 6
Conclusion 93
Bibliography 94
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