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研究生:吳秉恆
研究生(外文):Ping-Heng Wu
論文名稱:以鎖相迴路實現之寬頻頻率合成器
論文名稱(外文):Wideband PLL-Based Frequency Synthesizers
指導教授:楊清淵楊清淵引用關係
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:70
中文關鍵詞:數位電視頻率合成器
外文關鍵詞:DTVFrequency Synthesizer
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在本篇論文中,主要是探討寬頻鎖相迴路之設計,並實現一個除小數之頻率合成器來產生本地震盪訊號,且符合數位電視ATSC之規格。在寬頻鎖相迴路中,因為阻尼因子(ξ)和自然頻率(ωn)會隨著製程變異、溫度、供應電壓與除頻器除率N等而所變動,這將造成系統之不穩定。利用可適性頻寬的技術可以改善這個問題。
在頻率合成器的設計部分,可分為三個部份。
第一部分是使用自我偏壓之寬頻頻率合成器,藉由電流控制震盪器之線性增益,與大除數範圍之除頻器,達成可適性頻寬的特性。本晶片是使用TSMC 0.18um CMOS製程實現,量測的輸出頻率範圍可以從數百MHz到1.4GHz,鎖定時間為1.5us,晶片面積是1.4*1.4mm2。
第二部分使用相位補償的技術與頻帶選擇電路實現了一個低相位雜訊且寬頻之除小數頻率合成器來符合數位電視ATSC的規格。此晶片以TSMC 0.18um CMOS標準製程實現,量測結果在633MHz時可以得到-123dBc/Hz@1MHz offset, 最小通道寬度是6MHz,而鎖定時間為6us,功率消耗在1.8伏特時為40mW,晶片面積為1.2*1.2mm2。
最後一部分提出了一個快速鎖定頻率合成器具有可程式化之壓控震盪器增益,藉由MOS可變電容的特性,可對壓控震盪器增益加以程式化,並達成可適性頻寬特性。雙頻寬的設計可以更進一步達成快速的鎖定。本晶片以TSMC 0.18um CMOS製程實現,晶片面積為1.4*1.4mm2。
In this thesis, the main purpose is to design the wideband Phase-Lock Loop (PLL), and to realize a fractional-N frequency synthesizer providing the LO signal for Digital Television (DTV) ATSC standard. In the wideband PLL system, the damping factor (ξ) and natural frequency (ωn) are dependent with process, temperature, supply voltage and divisor N. This may cause the instability of system. However, the adaptive bandwidth technique can conquer this issue.
It can be divided into three parts about these frequency synthesizer designs.
First, by using the linear gain of current control oscillator and wide range frequency divider, a self-biased wideband frequency synthesizer is realized. This chip is fabricated in TSMC 0.18um CMOS process. The output frequency is from hundred MHz to 1.4GHz, the lock time is 1.5us, and the chip area is 1.4*1.4mm2.
Second, a low phase noise and fractional-N frequency synthesizer is realized by using phase compensation skill and band selector circuit to meet the DTV ATSC standard. This chip is fabricated in TSMC 0.18um CMOS process. The phase noise is -123dBc/Hz @ 1MHz at 633MHz, the channel space is 6MHz and settling time is 6us. The power consumption is 40mW under 1.8 supply voltage. The die size is 1.2*1.2mm2.
Finally, a fast lock frequency synthesizer with programmable KVCO is proposed. By using the characteristics of MOS varactor, the KVCO can be programmable, and another adaptive bandwidth is achieved. Moreover, the dual bandwidths make lock time faster. This work is fabricated in TSMC 0.18um CMOS, the die size is 1.4*1.4mm2.
Chapter1 Introduction ....................................1
1.1 Motivation ...........................................1
1.2 Overview of Thesis ...................................1
Chapter 2 Basic Concept of Phase-Lock Loop ...............3
2.1 Integer PLL-Based Frequency Synthesizer ..............3
2.2 Dynamical Analysis of PLL ............................4
2.2.1 Dynamical Analysis of Type I PLL ...................4
2.2.2 Dynamical Analysis of Charge Pump PLL ..............6
2.3 Adaptive Bandwidth PLL ...............................7
2.3.1 Introduced Adaptive Bandwidth PLL ..................7
2.3.2 Dynamical Analysis of Adaptive Bandwidth PLL .......9
2.4 Fractional-N Frequency Synthesizers .................11
2.4.1 Current Compensation Technique ....................13
2.4.2 Delta-Sigma Modulation Technique ..................13
2.4.3 Phase Compensation Technique ......................14
Chapter 3 Concept of Digital Television (DTV) Tuner .....17
3.1 Introduce of Digital Television (DTV) System ........17
3.2 Specification Definitions ...........................18
3.3 Tuner Structure .....................................19
3.3.1 Single Conversion Heterodyne ......................20
3.3.2 Up / Down Dual Conversion .........................21
3.3.3 Direct Conversion .................................22
3.4 Tuner LO Synthesizer Requirements ...................23
3.4.1 Phase Noise .......................................23
3.4.2 Tuning Range ......................................24
3.4.3 Channel Bandwidth .................................24
3.5 Conclusion ..........................................25
Chapter 4 A Wide-Band PLL-Based Frequency Synthesizer with Adaptive Dynamics .......................................26
4.1 Motivation ..........................................26
4.2 Architecture ........................................26
4.3 Circuit Implementation ..............................28
4.3.1 Current Control Oscillator (ICO) ..................28
4.3.2 Voltage to Current Converter (V to I converter) ...29
4.3.3 Programmable Frequency Divider ....................31
4.3.4 Charge Pump .......................................34
4.3.5 Phase-Frequency Detector (PFD) ....................35
4.3.6 Loop Filter (LF) ..................................36
4.3.7 System Simulation .................................36
4.4 Measurement .........................................39
4.4.1 Measurement Setup .................................39
4.4.2 Chip Photo ........................................39
4.4.3 Data Sheet ........................................40
4.4.3 Measurement Result ................................40
4.4.3.1 VCO Measurement .................................40
4.4.3.2 Divider Measurement .............................41
4.4.3.3 PLL Measurement .................................41
4.5 Conclusion ..........................................42
Chapter5 A Fractional-N Frequency Synthesizer for Digital TV Tuner ................................................43
5.1 Motivation ..........................................43
5.2 Architecture ........................................44
5.3 Circuit Implementation ..............................44
5.3.1 Voltage Control Oscillator ........................44
5.3.2 Band-Selecting Divider ............................46
5.3.3 Fractional-N Divider ..............................47
5.4 Measurement .........................................51
5.4.1 Measurement Setup .................................51
5.4.2 Data Sheet ........................................51
5.4.3 Measurement Result ................................52
5.5 Conclusion ..........................................56
5.6 Comparisons .........................................56
Chapter6 A Fractional-N Frequency Synthesizer with Programmable KVCO .......................................58
6.1 Motivation ..........................................58
6.2 Architecture ........................................59
6.3 Circuit Implementation ..............................61
6.3.1 VCO with Programmable KVCO ........................61
6.3.2 System Simulation .................................64
6.4 Conclusion ..........................................65
Chapter7 Conclusion .....................................66
Reference ...............................................67
[1] B.Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2000.
[2] J. Kim, M. A. Horowitz, G.Y. Wei, “Design of CMOS Adaptive-Bandwidth PLL/DLLs: A General Approach,” IEEE Transaction on Circuits and Systems II: Analog and Digital Signal Processing, Vol.50, NO.11, pp.860-869, Nov.2003.
[3] M. Mansuri, A. Hadiashar, C. K. K. Yang, “Methodology for On-Chip Adaptive Jitter Minimization in Phase-Locked Loops,” IEEE Transaction on Circuits and Systems-II: Analog and Digital Signal Processing, Vol.50, NO.11, pp.870-878, Nov.2003.
[4] J. Lee, and B. Kim, “A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control,” IEEE J. of Solid-State Circuits, Vol.35, NO.8, pp.1137-1145, August 2000.
[5] C.Y. Yang, and S.I. Liu, “Fast-Switching Frequency Synthesizer with a Discriminator-Aided Phase Detector,” IEEE J. of Solid-State Circuits, Vol.35, NO.10, pp.1445-1452, Oct. 2000.
[6] D. Byrd, C. Davis, and W. O. Keese, “A fast locking scheme for PLL frequency synthesizer,” National Semiconductor, Santa Clara, CA, Application Note, July 1995.
[7] Skyworks Solutions, Inc, “Basic of Dual Fractional-N Synthesizers/PLLs,” White Paper, May17, 2005.
[8] S.E. Meninger, M.H. Perrott, “A fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization- induced phase noise,” IEEE Transaction on Circuits and System-II: Analog and Digital Signal Processing, Vol.50, no. 11, Nov. 2003.
[9] B. Miller and R. J. Conley, “A Multiple Modulator Fractional Divider,” IEEE Transactions on Instrumentation and Measurement, Vol. 40, no. 3, June 1991.
[10] B. Bornoosh, A. Afzali-Kusha, R. Dehghani, M. Mehrara, S.M. Atarodi and M. Nourani, “Reduced complexity 1-bit higher-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis application,” IEEE Proc. Circuits Devices System, vol. 152, no. 5, October 2005.
[11] Y. Wu, S. Hirakawa, U.H. Reimers, and J.Whitaker, “Overview of digital television development worldwide,” Proc. IEEE, vol. 94, no. 1, pp. 8-21, Jan. 2006.
[12] United States Advanced Television Systems Committee, ATSC Digital Television Standard, Sept. 1995.
[13] European Telecommunications Standard Institute (ETSI), ETS 300 744 (1997): “Digital Broadcasting Systems for Television, Sound and Data Services; Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television,” 1997.
[14] Association of Radio Industries and Businesses (ARIB): “Terrestrial Integrated Services Digital Broadcasting (ISDB-T) Specifications of Channel Coding, Framing Structure, and Modulation,” Sept. 1998.
[15] I. Mehr, “Integrated TV Tuner Design for Multi-Standard Terrestrial Reception,” proc. IEEE RFIC, 2005, pp.75-78.
[16] R. Montemayor, "A 410-mW 1.22-GHz Downconverter in a Dual -Conversion Tuner IC for OpenCable Applications," IEEE, J. of Solid-State Circuits, Vol. 39, No. 4, April 2004.
[17] I. Mehr et al.,“A dual-conversion tuner for multi-standard terrestrial and cable reception,” in Symp.VLSI Circuits Dig.Tech. Papers, June 2005, pp.340-343.
[18] I. Vassiliou, K. Vavelidis, S. Bouras, S. Kavadias, Y. Kokolakis, G. Kamoulakos, A. Kyranas, C. Kapnistis, and N. Haralabidis, “A 0.18μm CMOS Dual-Band Direct-Conversion DVB-H Receiver,” IEEE ISSCC Dig. Tech. Papers, Feb. 2006, paper no. 33.1.
[19] M. Womac, A. Deiss, T. Davis, R. Spencer, B. Abesingha, and P. Hisayasu,“Dual-band Single-Ended-Input Direct-Conversion DVB-H Receiver,” IEEE ISSCC Dig. Tech. Papers, Feb. 2006, paper no. 33.3.
[20] B. Razavi, “Oscillator in RF Microelectronics.” NJ: Prentice Hall, 1998, p.216-p.217
[21] M. Marutani, H. Anbutsu, M. Kondo, N. Shirai, H. Yamazaki, Y. Watanabe, “An 18mW 90 to 770MHz synthesizer with agile auto-tuning for digital TV-tuners”, IEEE ISSCC Dig. Tech. Papers, Feb., 2006, pp. 681- 690.
[22] J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, M. Shankaradas, “Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL” , IEEE J. of Solid-State Circuits, Vol.38, pp. 1795 – 1803, Nov. 2003.
[23] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques”, IEEE J. of Solid-State Circuits, Vol.31, pp.1723 – 1732, Nov. 1996.
[24] Y. H. Chuang, S. L. Jang, J. F. Lee, S. H, Lee, “A low voltage 900MHz voltage controlled ring oscillator with wide tuning range,” IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004.
[25] I. A. Young, J. K. Greason, K. L. Wong, “A PLL clock generator with 5 to 10 MHz of lock range for microprocessors”, IEEE J. of Solid-State Circuits, vol.27, pp. 1599-1607, Nov. 1992.
[26] G. Moon, M. E. Zaghloul, R.W. Newcomb, “An enhancement-mode MOS voltage-controlled linear resistor with large dynamic range”, IEEE Trans. On Circuits and Systems, Vol.37, no. 10, pp.1284-1288, Oct. 1990.
[27] C. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, Z. Wang, “A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology”, IEEE J. of Solid-State Circuits, Vol.35, pp.1039-1045, July 2000.
[28] J. S. Lee, M. S. Keel, S. I. Lim, S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops”, Electronics Letters, pp. 1907-1908, Nov. 2000.
[29] ATSC Digital Television Standards, A/53 Part 1~6, Jan. 3, 2007.
[30] Y. C. Yang, S. A. Yu, T. Wang, S. S. Lu, “A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell,” IEEE Microw. Wireless Compon. Lett., vol. 15, no. 11, Nov. 2005.
[31] C. C. Boon, M. A. Do, K. S. Yeo, J. G. Ma, ” Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction,” IEEE Tran. On Circuit and System I, June 2005.
[32] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-v Dual-Modulus Divide-by-128/129 Prescaler in 0.7-μm CMOS,” IEEE J. of Solid-State Circuits, vol.31, no7, pp890-897, Jul. 1996.
[33] W. Rhee and A. Ali, “An on-chip phase compensation technique in fractional-N frequency synthesis,” IEEE Int. Sym. Circuits & System, May 1999, pp. 363-366.
[34] C. Y. Yang, J. W. Chen, and M. T. Tsai, “A high-frequency phase-compensation fraction-N frequency synthesizer,” IEEE Int. Sym. Circuits & System, May 2005, pp. 5901-5904.
[35] Y. C. Yang, F. T. Lee, and S. S. Lu, “A single-VCO fractional-N frequency synthesizer for digital TV tuners,” IEEE Int. Microw. Sym., Jun. 2007, pp. 1545-1548.
[36] E. Y. Sung, K. S. Lee, D. H. Baek, Y. J. Kim, B. H. Park, “A wideband 0.18-μm CMOS ΔΣ fractional-N frequency synthesizer with a single VCO for DVB-T,” IEEE Asian Solid-State Circuits Conf., Nov.2005, pp. 193-196.
[37] D. Hauspie, E. C. Park, and J. Craninckx, "Wideband VCO With Simulataneous Switching of Frequency Band, Active Core, and Varactor Size", IEEE, J. of Solid-State Circuits, Vol. 42, NO.7, pp.1472-1480, July 2007.
[38] S. S. Broussev, T. A. Lehtonen, N. T. Tchamov, "A Wideband Low Phase-Noise LC-VCO With Programmable KVCO", IEEE Microwave and Wireless Components Letters, Vol.17, No.4, pp.274-276, April 2007.
[39] S. Shin; K. Lee; S. M. Kang, "4.2W CMOS Frequency Synthesizer for 2.4GHz ZigBee Application with Fast Settling Time Performance," IEEE, Microwave Symposium Digest, June 2006.
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