( 您好!臺灣時間:2021/08/02 13:50
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::


研究生(外文):Jiun-Tang Tseng
論文名稱(外文):Scalable FFT Processor Designs with Dynamic Precision Scaling for Multi-Standard Applications
外文關鍵詞:FFTBlocking Floating PointOFDMMIMO
  • 被引用被引用:0
  • 點閱點閱:89
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
針對以正交分頻多工為基礎之通訊系統,提出一種可伸縮性之快速傅利葉核心設計。此核心組成主要可分為兩種模組為Split-Radix-2/4/8 MDC模組與Radix2/4 MDC模組,使用兩個基本模組可以組成任意點數的FFT運算核心,加上回授的技術共用複數乘法器與旋轉因子查表電路減少面積的消耗,搭配前置資料穿插排程電路有效利用N/2點等待時間,並且對資料加以排程,同時使資料以穿插方式運算且改善傳統MDC架構在硬體使用效率上的不足,使整體核心之工作效率皆為100%。再加上區塊動態調整精確度的方式以群組的方式共同使用相同的指數,減少位移電路複雜度與只儲存指數的記憶體大小,經過模擬與實做結果證明可減少2位元的字元,減少10%晶片面積且能保持相同的量化誤差比,本論文中提出兩個架構一是最高支援512點scalable FFT核心以TSMC 0.18um 1P6M實現晶片面積為1.9x1.9mm2在100/50MHz執行速度下功率消耗為108.1mW,另一架構為最高支援2048點高傳輸率的scalable FFT核心,在102.8/51.4 MHz速度執行下其符合IEEE 802.15.3a標準要求409.6M Samples/sec的條件。
In this thesis, we propose a novel scalable FFT processor design capable of handling various transform sizes and data channels for multi-standard MIMO processing. The basic building blocks are split-radix 2/4/8 FFT modules in a modified MDC (multi-path delay commutator) form, pre-ordering data buffer, radix-2 butterfly module and twiddle factor module. Via proper data flow reconfiguration plus two alternative working frequencies, the processor can support various transform sizes plus 1 to 4 MIMO channels. The iterative compuaution scheme adopted in one of the split-radix 2/4/8 FFT module also facilitates the hardware sharing of complex multiplier and twiddle factor table. With the careful data scheduling in pre-ordering buffer, the hardware utilization of the FFT kernel is kept as 100% under various working modes. To reduce the circuit complexity, we further propose a block based dynamic scaling scheme. It can dynamically slide the position of data window by at most 2-bit. The width of line buffer and data path can thus be reduced accordingly. Despite the extra circuit employed in dynamic scaling scheme, simulation results indicate the overall chip area can be reduced by 10% without any additional quantization error loss. Finally, two versions of the scalable FFT processor designs using TSMC 0.18um 1P6M CMOS process are accomplished in this thesis. The first one can support from 64 up 512-point FFT computations The experimental results show that it has a core size 1.9x1.9mm2, and a power consumption of 108.1mW at 100/50MHz. The second design with parallel butterfly modules can support up to 2048-point computations and the highest processing speed can meet the throughput demand (409.6 MSamples/sec condition at 108.2/51.4MHz) IEEE 802.15.3a standard.
誌謝 ii
摘要 iii
Abstract iv
目錄 v
圖目錄 vii
表目錄 ix
第1章 緒論 1
1.1. 研究背景 1
1.2. OFDM系統介紹 2
1.3. 各OFDM通訊系統之FFT參數介紹 4
1.4. 研究動機 5
1.5. 章節介紹 5
第2章 FFT/IFFT演算法及架構介紹 6
2.1. DFT/IDFT演算法特性 6
2.2. FFT演算法 7
2.2.1. Radix-2演算法 7
2.2.2. Radix-r、Radix-2i演算法 7
2.2.3. Split-Radix演算法 8
2.3. FFT演算法總結 9
2.4. 以記憶體為主之運算架構 10
2.5. 管線化之運算架構 12
2.5.1. Radix-2 SDF架構 12
2.5.2. Radix-r/Radix-2i SDF架構 13
2.5.3. Radix-2 MDC架構 15
2.5.4. Radix-r/Radix-2i MDC架構 16
2.5.5. 管線化架構之比較 18
第3章 可伸縮性FFT核心硬體架構設計 20
3.1. Scalable FFT硬體架構 20
3.2. Scalable FFT kernel之基本架構 20
3.3. Scalable FFT kernel各模組電路 22
3.3.1. Data Preordering電路 22
3.3.2. Split-Radix-2/4/8 MDC運算模組 27
3.3.3. Split-Radix-2/4/8 MDC回授運算模組 29
3.3.4. 旋轉因子產生器 31
3.4. Scalable FFT組態設計 33
3.4.1. 64點FFT組態 34
3.4.2. 512點FFT組態 36
3.4.3. 128點FFT組態 37
3.4.4. Scalable FFT組態 38
3.4.5. 任意點數FFT組態 38
3.5. High throughput Scalable FFT設計 41
3.6. Scalable FFT 架構設計方法 42
第4章 Scalable FFT之精確度動態調整設計 45
4.1.1. Block size 區塊大小模擬分析 46
4.1.2. shift step size位移區間大小模擬分析 47
4.1.3. limits of Maximum accumulated Shift累積位移次數限制模擬分析 48
4.1.4. dynamic scaling動態調整電路設計 49
4.1.5. 動態調整與平行處理電路設計 53
第5章 電路模擬與合成結果 54
5.1. 驗證工具與資料型態 54
5.2. Scalable FFT kernel合成結果 55
5.2.1. 512點FFT版本 55
5.2.2. 2048點FFT與動態調整版本 57
5.2.3. 2048點FFT動態調整面積比較 59
5.3. Scalable FFT kernel功率消耗分析 61
5.3.1. 512點FFT版本 61
5.3.2. 2048點FFT與動態調整版本 62
第6章 結論 63
參考文獻 64
[1]Byung G. Jo, Myung H. Sunwoo, “New Continuous-Flow Mixed-Radix (CFMR) FFT Processor Using Novel In-Place Strategy,” IEEE Trans. On Circuits and Systems, Volume 52, Issue 5, pp.911 – 919, May 2005.
[2]VLSI-oriented FFT algorithm and implementation,” ASIC Conference, pp.337 – 341, Sept. 1998.
[3]Yu-Wei Lin, Hsuan-Yu Liu, Chen-Yi Lee, “A Dynamic Scaling FFT Processor for DVB-T Applications,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Volume 39, Issue 11, pp. 2005 – 2013, Nov. 2004.
[4]Yun-Nan Chang, Keshab K. Parhi, “An Efficient Pipelined FFT Architecture,” IEEE Trans. On Circuits and Systems, Volume 50, Issue 6, pp.322 – 325, June 2003.
[5]Haining Jiang, Hanwen Luo, Jifeng Tian and Wentao Song, “Design of an Efficient FFT Processor for OFDM Systems,” IEEE Trans. On Consumer Electronics, Volume 51, Issue 4, pp.1099 – 1103, Nov. 2005.
[6]T. Sansaloni, A. Pe′rez-Pascual, V. Torres and J. Valls, “Efficient pipeline FFT processors for WLAN MIMO-OFDM systems,” Electronics Letters, Volume 41, Issue 19, pp.1043 – 1044, Sept. 2005.
[7]Pandey, R., Bushnell, M.L., “Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System,” International Conference on VLSI Design, pp.121 – 126, Jan. 2007.
[8]Lee, H.-Y., Park, I.-C, “Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing,” IEEE Trans. on Circuits and Systems, Volume 54, Issue 4, pp.889 – 900, April 2007.
[9]Guichang Zhong, Fan Xu, Willson, A.N., Jr., “A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring,” IEEE Journal of Solid-State Circuits, Volume 41, Issue 2, pp.483 – 495, Feb. 2006.
[10]Young-jin Moon, Young-il Kim, “A mixed-radix 4-2 butterfly with simple bit reversing for ordering the output sequences,” International Conference Advanced Communication Technology, Volume 3, pp.4, Feb. 2006.
[11]Chua-Chin Wang, Jian-Ming Huang, Hsian-Chang Cheng, “A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers,” IEEE Trans. on Consumer Electronics, Volume 51, Issue 1, pp.28 – 32, Feb. 2005.
[12]Sansaloni, T., Perez-Pascual, A., Valls, J., “Area-efficient FPGA-based FFT processor,” Electronics Letters, Volume 39, Issue 19, pp.1369 – 1370, Sept. 2003.
[13]M. Hasan, T. Arslan, J.S. Thompson, “A Novel Coefficient Ordering based Low Power Pipelined Radix-4 FFT Processor for Wireless LAN Applications,” IEEE Trans. On Consumer Electronics, Volume 49, Issue 1, pp. 128 – 134, Feb. 2003.
[14]Bernard, E., Krammer, J.G., Sauer, M., Schweizer, R., “A pipeline architecture for modified higher radix FFT,” International Conference on Acoustics, Speech, and Signal Processing, Volume 5, pp.617 – 620, March 1992.
[15]Bidet, E., Castelain, D., Joanblanq, C., Senn, P., “A fast single-chip implementation of 8192 complex point FFT,” IEEE Journal of Solid-State Circuits, Volume 30, Issue 3, pp.300 – 305, March 1995.
[16]Prabhu, J.A., Zyner, G.B., “167 MHz radix-8 divide and square root using overlapped radix-2 stages,” Symposium on Computer Arithmetic, pp.155 – 162, July 1995.
[17]Yunho Jung, Hongil Yoon, Jaeseok Kim, “New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications,” IEEE Transactions on Consumer Electronics, Volume 49, Issue 1, pp.14 – 20, Feb. 2003.
第一頁 上一頁 下一頁 最後一頁 top