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研究生:邱薇蓉
研究生(外文):Wei-Rong Ciou
論文名稱:低複雜度脈波觸發型正反器設計與分析
論文名稱(外文):Designs and analyses of low complexity pulse triggered flip-flops
指導教授:黃穎聰黃穎聰引用關係
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:83
中文關鍵詞:低功率正反器脈波觸發
外文關鍵詞:Low PowerFlip-FlopPulse-Triggered
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在本篇論文中分別提出兩種不同的多功能脈波觸發型正反器;第一種為雙重脈波模式觸發型正反器(dual-mode pulse-triggered Flip-Flop),其電路可提供單緣脈波觸發和雙緣脈波觸發兩種工作模式,此雙重脈波模式觸發型正反器是第一個利用傳導電晶體邏輯(pass transistor logic,PTL)所設計之電路,電路中利用簡易的設計成功的解決因PTL電路所造成臨界電壓降低的問題(threshold voltage loss),此電路比其他正反器電路擁有更低之功率消耗和佈局面積,電路設計使用脈波產生器(pulse generator)和準位拴鎖器(level sensitive latch)組成使用AND-XNOR邏輯模組之雙重脈波模式觸發型正反器(dual-mode pulse-triggered flip-flop using unified AND-XNOR logic module,DMP-FF)。整體性能比較的電路包含一個使用於Xilinx FPGAs的雙重正反器(Xilinx dual-mode flip-flop)和三種僅支援一種動作模式之脈波觸發型正反器;所提出之電路比起雙重主僕式正反器擁有更小的佈局面積和較佳的功率消耗及工作頻率,DMP-FF電路有較低的電路複雜性和兩種工作模式,此外,比起其他僅有一種工作模式之電路有較好的各種參數和功率消耗。
使用一樣的電路設計技巧,本篇論文提出第二種具有低複雜度的脈波產生器電路和可程式化的正反器(programmable pulse-triggered flip-flop using two AND logic tree with disable function,PPT-FF);此電路使用最少的電晶體數成功合併三種不同的觸發模式和時脈除能(disable)的功能,對於時脈系統來說可同時降低電路複雜性和負載電容;其模擬結果顯示出此電路擁有極佳的效能。
文中所有的正反器模擬均為佈局後的模擬(post-layout simulation)數據,採用TSMC 0.18μm CMOS process technology的製程完成;由模擬結果可知DMP-FF的各種效能比上其他僅有一種觸發模式的電路都有較佳的表現;而PPT-FF的模擬結果中也顯示整體電路的功率延遲積可以產生比傳統主僕式的可程式化正反器節省二到六倍的效果。
In this thesis, we proposed two novel pulse-triggered flip-flop designs for functional versatility. The first circuit is a dual-mode flip-flop, i.e. single- and double-edge triggered modes. A dual-mode pulse generator using pass transistor logic (PTL) is derived first. Both threshold voltage loss and poor driving capability problems common in PTL design are successfully resolved while the circuit simplicity is kept. Combining the pulse generator design with a level sensitive latch leads to a dual-mode pulse-triggered flip-flop (DMP-FF) design. Extensive performance comparisons, including with one programmable FF design for FPGAs and with three other single mode pulse-triggered FF designs and, are conducted. The proposed design, with a much smaller layout area, edges over the programmable FF design significantly in speed and power consumption. The proposed design, bearing similar circuit complexity plus the advantage of dual mode operations, also performs equally well as other single mode designs do in various AC parameters and power consumption.
Besed on the same circuit technique, another low complexity pulse generator design for programmable pulse-triggered flip-flop using two AND logic tree with disable function (PPT-FF) is next presented. With the minumin number of transistors, this design successfully incorporates 3 triggering modes and disable function (clock gating). Both circuit complexity and loading capacitance of clock tree system can thus be reduced. Simulation results are given to show its performance edges.
The comparisons of all data are conducted using post-layout simulations in TSMC 0.18μm CMOS process technology. Simulation results also indicate that the DMP-FF can rival or even outperform other single- or dual-mode designs in various performance indexes. The PPT-FF results have demonstrated its ability to achieve up to 2 and 6 times power consumption and power-delay-product saving compared with master-slave based design.
中文摘要 i
ABSTRACT ii
目錄 iii
表目錄 vi
圖目錄 vii
第1章 緒論 1
1-1 研究動機與背景 1
1-1-1 功率消耗 1
1-1-1-1 動態功率消耗 2
1-1-1-2 切換機率分析 3
1-1-1-3 靜態功率消耗 4
1-1-2 使用正反器電路達到系統低功耗之設計技巧 6
1-2 研究方法及流程 6
1-2-1 正反器之分類 7
1-2-2 單緣觸發型正反器 9
1-2-3 雙緣觸發型正反器 10
1-2-4 正反器之運作時序 12
1-3 內容大綱 12
第2章 脈波觸發型及可程式化正反器 14
2-1 前言 14
2-2 各式栓鎖器之介紹 14
2-3 外加式脈波觸發型正反器 19
2-3-1 外加式單緣觸發型正反器 20
2-3-2 外加式雙緣觸發型正反器 21
2-4 嵌入式脈波觸發型正反器 24
2-4-1 嵌入式單緣脈波觸發型正反器 24
2-4-2 嵌入式雙緣脈波觸發型正反器 25
2-5 主僕式可程式化正反器 26
2-5-1 Xilinx雙重主僕式正反器 26
2-5-2 Xilinx可程式化主僕式正反器 27
第3章 使用AND-XNOR邏輯模組之雙重脈波模式觸發型正反器 30
3-1 前言 30
3-2 雙重脈波模式產生器之電路介紹 30
3-3 雙重脈波模式觸發型正反器之電路介紹 34
3-4 模擬環境設定 36
3-5 脈波產生器模擬結果 37
3-6 單一位元正反器模擬結果 38
3-7 正反器多位元並聯模擬結果 45
3-8 本章結論 52
第4章 使用AND邏輯模組之可程式化脈波觸發型正反器 53
4-1 前言 53
4-2 可程式化脈波觸發型正反器之電路介紹 53
4-3 模擬環境設定 56
4-4 單一位元模擬結果 56
4-5 正反器多位元並聯模擬結果 60
4-6 本章結論 66
第5章 提出的兩種正反器之晶片實現及分析 67
5-1 前言 67
5-2 設計流程 67
5-3 晶片設計考量 69
5-3-1 面積考量 69
5-3-2 功率量測考量 70
5-4 晶片之模擬結果驗證 71
5-4-1 雙重脈波模式觸發型正反器 71
5-4-2 可程式化脈波觸發型正反器 73
5-5 晶片佈局 74
5-6 晶片之實測結果 76
第6章 結論 79
參考文獻 80
參考文獻
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