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研究生:李昆憲
研究生(外文):Kun-Hsing Li
論文名稱:應用於H.264/AVC之幀內畫面編碼系統分析及電路架構設計與實現
論文名稱(外文):Analysis and Architecture Design of H.264/AVC Intra Frame Coder
指導教授:賴永康
指導教授(外文):Yeong-Kang Lai
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:72
中文關鍵詞:H.264幀內畫面編碼器H.264幀內預測產生器
外文關鍵詞:H.264 Intra Frame CoderH.264 Intra Prediction Generator
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在本篇論文中,我們提出了一個工作於62.5MHz和每秒30張畫面HD720P解析度的8平行度H.264幀內畫面編碼架構。而且我們提出了單一核心之多重轉換架構,可以同時產生整數轉換和Hadamard轉換的結果,來達到減少執行週期與維持影像品質。同時我們在影像編碼的排程上,提出了I4MB/I16MB交錯的排程,來使得硬體使用效率大大的提昇。而在幀內預測架構上,我們使用了種子(seed)運算的方法,使得幀內預測影像可以在2個週期完成4×4影像區塊。在編碼架構上,我們採用了記憶體交錯(Ping-Pong mode)的技術,使得預測階段與編碼階段得以分離,如此才可完成HD720P畫面的編碼。而在基於上下文之可變長度編碼(CAVLC)架構上,我們改善了先前架構過長的掃描週期,採用簡單的邏輯運算,運算出需編碼的位置,使得編碼週期大大的縮短。最後實作結果顯示本架構可工作於62.5MHz的頻率下,完成HD720P@30fps的影像壓縮而晶片面積為1.25×1.25mm2。而且我們架構的模式判斷是採用Hadamard Transfrom的相減轉換絕對值之和(SATD),而且我們的架構有支援I16MB平面模式的預測畫面。若將我們的架構應用於SD(720×480)畫面上的話,我們的架構只需工作於23.4MHz即可完成,因此可以將此電路架構運用於多種影像相關的電子產品上。
In this paper, we proposed an HD720P@30fps H.264 intra frame coder architecture with eight parallel processing elements. And we proposed unique kernel multi-transform architecture, it could generate results of integer transform and Hadamard transform simultaneously, and reach to reduce operation period and keep image quality. In our image coding schedule, we proposed I4MB/I16MB interleaving schedule, to increase hardware utilization. In the intra prediction architecture, we use seed method to operate result of intra prediction, and achieve 4×4 block predictor at two cycles. In the entropy coding architecture, we adopted memory interleaving technology to separate prediction phase and coding phase, and it could achieve HD720P frame coding. In CAVLC architecture, we improve the longer scan period of the previous architecture. Also we utilize simple logic operations to compute the address of coding and reduce the coding period. According to the experimental results, the chip implementation results show that proposed architecture can work at 62.5MHz to achieve HD720P@30fps image compression, and the chip size is 1.25×1.25mm2. In addition, the mode decision of our architecture adopted Hadamard transform (SATD), and our architecture can support prediction frame of I16MB plane mode. If the proposed architecture is applied to the SD(720×480)specification, it can perform 720×480@30fps in real time at 23.4MHz working frequency. Therefore, the proposed architecture can be utilized in various mobile video applications.
第一章 引言 - 1 -
1.1 視訊壓縮標準(Video Compression Standard) - 1 -
1.2 論文組織 - 3 -
第二章 H.264/AVC視訊壓縮標準 - 4 -
2.1 前言 - 4 -
2.2 可變區塊大小的移動補償(variable block size Motion Compensation) - 5 -
2.3 多重參考畫面的移動補償(multiple reference pictures for Motion Compensation) - 6 -
2.4 內部去區塊濾波器(in-loop Deblocking Filter) - 6 -
2.5 幀內畫面預測(intra-frame prediction) - 7 -
2.5.1 4X4亮度預測模式(4X4 Luma Prediction Modes) - 7 -
2.6 H.264/AVC轉換(H.264/AVC Transform) - 10 -
2.6.1 4X4整數轉換(4X4 integer transform) - 10 -
2.6.2 4X4 hadamard轉換(4X4 hadamard transform) - 12 -
2.6.3 2X2 hadamard轉換(2X2 hadamard transform) - 12 -
2.6.4 反轉換(inverse transform) - 12 -
2.7 量化與反量化(quantisation and inverse quantisation) - 13 -
2.7.1 量化(quantisation) - 13 -
2.7.2 反量化(inverse quantisation) - 14 -
2.8 熵編碼(entropy coding) - 15 -
2.9 幀內模式決定(intra mode decision) - 16 -
2.10 幀內畫面編碼(intra frame coding) - 16 -
第三章 H.264/AVC幀內畫面編碼架構回顧與探討 - 18 -
3.1 幀內畫面編碼架構討論 - 18 -
3.2 典型幀內畫面編碼架構比較 - 23 -
第四章 H.264/AVC幀內畫面編碼硬體架構之設計 - 25 -
4.1 設計挑戰 - 25 -
4.2 系統架構演算法分析 - 27 -
4.3 硬體平行度分析 - 32 -
4.4 幀內編碼整體之架構 - 33 -
4.5 幀內預測器之架構 - 37 -
4.5.2 I16MB預測 - 38 -
4.5.3 幀內預測器整體之架構 - 41 -
4.6 2D多重轉換架構和2D多重反轉換架構 - 44 -
4.6.1 2D單一核心之多重轉化架構 - 44 -
4.6.2 2D多重反轉換架構 - 47 -
4.7 量化架構和反量化架構 - 48 -
4.7.1 量化架構 - 49 -
4.7.2 反量化架構 - 51 -
4.8 熵編碼架構 - 52 -
4.8.1 指數型哥倫布編碼架構 - 52 -
4.8.2 基於上下文之可變長度編碼架構 - 53 -
4.8.3 熵編碼之整體架構 - 56 -
第五章 晶片實作驗證與效能分析 - 57 -
5.1 晶片設計流程 - 57 -
5.2 晶片的規格 - 58 -
5.3 程式碼含概率 - 61 -
5.4 晶片實作結果 - 62 -
5.5 比較與貢獻 - 64 -
5.6 FPGA驗證實作 - 66 -
第六章 結論 - 68 -
參考文獻(Reference) - 69 -
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