在積體電路製程中，常常需要在晶圓上做出細微尺寸的圖案，而這些圖案的形成方式，乃是使用蝕刻技術，將微影技術所產生的光阻圖案，無誤的轉移到光阻底下的材質上。所謂的蝕刻技術，包含了所有將材質整面均勻移除的等向性蝕刻，或是有圖案的選擇性部分去除之非等向性蝕刻。而接觸層電漿蝕刻製程即是屬於非等向性蝕刻。在製程線寬越縮越小的情況下，如何有效且快速的控制接觸層線寬也就更顯得重要。
本文主要研究底層抗反射介電覆膜，蝕刻程式參數變化對接觸層線寬的調整能力。其內容在研究不同的C4F8氣體流量、製程時間與製程壓力條件下。對接觸層線寬的調整效果，並且從線寬與晶圓電性測試的結果分析其相關性。
實驗結果顯示，在氣體C4F8原始12sccm條件下，氣體流量增加1sccm對接觸層線寬約減小1.14nm(約1.6%) ;在製程時間原始120秒條件下，製程時間減少6秒對接觸層線寬約減小0.76nm(約1.06%) ;在製程壓力原始130mTorr條件下，製程壓力增加10mTorr對接觸層線寬約減小0.34nm(約0.47%)。另外線寬每減小1nm，電性接觸電阻的阻值增加0.76Ω。
從上述實驗結果可定論，抗反射介電覆膜蝕刻程式參數影響接觸層線寬最大的是C4F8氣體流量及製程時間，再來是製程壓力。線寬越小電性測試的接觸電阻阻值越大。

In the integrated circuit manufacturing process, Patterns of small sizes often needs to be formed on the wafer. The method of pattern formation is to use developers to remove the exposure photo resist so that pattern can be directly transferred to wafer. Etching method is the technology used, including isotropic etching and non-isotropic etching. The contact plasma etching process is a non-isotropic etching. As the process pattern dimension shrinks gradually, it is important to know how to control the contact line width effectively and fast.
In this study, the change of bottom antireflective coating etching recipe parameter to adjust the contact line width is the main focus. Comparing parameter change along with the contact line width, three factors are considered, namely differences of C4F8 flow, process time, and process pressure. Furthermore, the correlation between contact line width and wafer electrical test result is also analyzed.
According to the experiment results, firstly increasing the C4F8 gas flow by 1 sccm from 12sccm, decreases the line width approximately 1.14nm (~1.6%); Secondly, increasing process time by 6 seconds from 120seconds, decreases the line width approximately 0.76nm(~1.06%); Lastly, increasing the process pressure by 10mTorr from 130mTorr, decreases the line width approximately 0.34nm(~0.47%).Decreasing the contact line width by 1nm will cause wafer electrical test contact resistance to increase by0.76Ω
From the results above, it can be concluded that C4F8 gas flow and process time is the key factor for line width regulation, then the process finally by the pressure. The smaller line width is higher electrical test resistance presents.

摘要Ⅰ
AbstractⅡ
誌謝IV
目錄V
表目錄IX
圖目錄X
第一章 導論1
1.1 前言1
1.2 研究動機2
1.3 研究內容3
第二章 原理與文獻回顧4
2.1 半導體製程介紹4
2.2 蝕刻製程介紹4
2.2.1 蝕刻率(Etch Rate )與均勻度(Uniformity)5
2.3 接觸層製程介紹5
2.4 電漿簡介6
2.5 底層抗反射介電覆膜簡介6
2.5.1 底層抗反射層6
2.5.2 抗反射層材料9
2.6 底層抗反射介電覆膜(BARC)應用介紹10
2.6.1 製程氣體對線寬控制的機制10
2.6.2 製程壓力對線寬控制的機制11
2.7 電性測試(WAT)簡介12
2.7.1 電性測試介紹12
2.7.2 電性中的接觸電阻測試介紹13
2.7.3 接觸層線寬與電性的相關性機制14
2.8 單片晶圓乾蝕刻機蝕刻機制14
2.8.1 磁場增強式反應性離子蝕刻單片晶圓乾蝕刻機介紹15
2.8.2 高密度的電漿系統(HDP)單片晶圓乾蝕刻機介紹15
第三章 實驗材料設計與方法18
3.1 實驗設計與方法18
3.2 實驗材料18
3.2.1 十二吋矽晶圓片18
3.2.2 光阻劑與抗反射介電覆膜19
3.3 實驗設備193.3.1 單片晶圓乾蝕刻機19
3.3.2 化學氣相沉積機20
3.3.3 步進機(TEL)+曝光機(ASML)20
3.3.4 線寬量測機20
3.3.5 電性量測機21
3.4 抗反射介電覆膜蝕刻程式22
3.5 洞的寬度量測22
3.6 實驗流程24
3.6.1 抗反射層C4F8氣體流量在單片晶圓乾蝕刻機中對接觸層線寬的影響25
3.6.1.1 實驗目的25
3.6.1.2 實驗步驟25
3.6.2 抗反射層製程時間在單片晶圓乾蝕刻機中對接觸層線寬的影響26
3.6.2.1 實驗目的26
3.6.2.2 實驗步驟26
3.6.3 抗反射層製程壓力在單片晶圓乾蝕刻機中對接觸層線寬的影響26
3.6.3.1 實驗目的27
3.6.3.2 實驗步驟27
第四章 結果與討論28
4.1 C4F8氣體流量在單片晶圓乾蝕刻機中對接觸層線寬實驗結果與討論28
4.1.1 不同C4F8氣體流量對接觸層線寬結果28
4.1.2 不同C4F8氣體流量對抗反射層蝕刻率實驗結果28
4.1.3 抗反射層蝕刻程式不同C4F8流量送切剖面圖結果29
4.1.4 抗反射層蝕刻程式不同C4F8流量對電性實驗結果29
4.2 製程時間在單片晶圓乾蝕刻機中對接觸層線寬實驗30
4.2.1 不同製程時間對接觸層線寬結果30
4.2.2 抗反射層蝕刻程式不同製程時間對電性實驗結果30
4.3 製程壓力在單片晶圓乾蝕刻機中對接觸層線寬實驗結果與討論30
4.3.1 抗反射層蝕刻程式不同製程壓力對接觸層線寬結果31
4.3.2 抗反射介電覆膜蝕刻程式不同製程壓力對電性實驗結果31
4.4 接觸層線寬對晶圓電性測試接觸電阻相關性討論31
4.4.1 線寬對晶圓電性測試接觸電阻相關性結果31
第五章 結論與建議33
參考文獻36
表3.1 正光阻成份42
表3.2 抗反射介電覆膜蝕刻原始程式42
表3.3 抗反射介電覆膜蝕刻原始程式實驗結果43
表3.4 抗反射介電覆膜蝕刻程式C4F8氣體流量變化實驗44
表3.5 抗反射介電覆膜蝕刻程式C4F8氣體流量變化對電性影響44
表3.6 抗反射介電覆膜蝕刻程式蝕刻時間變化實驗45
表3.7 抗反射介電覆膜蝕刻程式蝕刻時間變化對電性影響45
表3.8 抗反射介電覆膜蝕刻程式蝕刻壓力變化實驗46
表3.9 抗反射介電覆膜蝕刻程式蝕刻壓力變化對電性影響46
表4.1 抗反射介電覆膜蝕刻程式C4F8不同流量變化送切剖面圖結果47
圖2.1 晶圓廠製造流程(Wafer Foundry)48
圖2.2 接觸層製程流程圖49
圖2.3 電漿內部各物種之行為50
圖2.4 底層抗反射層51
圖2.5 光強度在阻劑中隨厚度分佈的情形51
圖2.6 刻痕效應示意圖52
圖2.7 接觸層蝕刻剖面圖52
圖2.8 製程氣體對線寬反應機制53
圖2.9 接觸層電性測試圖53
圖2.10 接觸層電性測試推算54
圖2.11 RIE永久磁鐵與磁力線圈54
圖2.12 HDP高密度電漿系統55
圖3.1 單片晶圓乾蝕刻機反應室55
圖3.2 單片晶圓乾蝕刻機組成56
圖3.3 電漿輔助化學氣相沉積系統PECVD(諾發系統公司製造)57
圖3.4 低壓化學氣相沉積系統SACVD(應用材料公司製造)57
圖3.5 步進機(東京威力科創公司製造)58
圖3.6 曝光機(艾司摩爾公司製造)58
圖3.7 光學膜厚儀(日立製造)59
圖3.8 電性量測機(ACCRETECH製造)59
圖3.9 光學膜厚儀構造圖(日立製造)60
圖3.10 CD-SEM影像60
圖4.1 抗反射介電覆膜蝕刻程式C4F8流量變化對線寬影響61
圖4.2 抗反射介電覆膜蝕刻程式C4F8流量變化對抗反射介電覆膜蝕刻
率影響62
圖4.3 抗反射介電覆膜蝕刻程式不同C4F8流量送切剖面圖63
圖4.4 不同C4F8流量條件的線寬對電性阻值相關性63
圖4.5 不同製程時間條件對線寬相關性64
圖4.6 不同製程時間條件的線寬對電性阻值相關性65
圖4.7 不同製程壓力條件對線寬相關性66
圖4.8 不同製程壓力條件的線寬對電性阻值相關性67
圖4.9 65奈米所有實驗晶片線寬對電性阻值相關性圖67
圖4.10 90奈米線寬對電性阻值相關性圖68
圖4.11 0.13微米線寬對電性阻值相關性圖68

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