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研究生:陳羿君
研究生(外文):Yi-Jiun Chen
論文名稱:新型低功率兩階段快閃式類比數位轉換器
論文名稱(外文):A Novel Low Power Two-Step Flash Analog-to-digital converter
指導教授:賴源泰
指導教授(外文):Yen-Tai Lai
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:47
中文關鍵詞:快閃式類比數位轉換器低功率
外文關鍵詞:low powerflash ADC
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近年來,由於製程和無線通訊方面的快速發展,速度和功率的需求越來越重,在速度上的考量,快閃式類比數位轉換器無疑是最優先的選擇,但是快閃式類比數位轉換器的面積和功率會隨著解析度而成倍數的成長,所以無法達到高解析度的設計。因此,一個具有高速、高解析度、低功率消耗的類比數位轉換器是許多人的研究目標。然而在現實上的考量,僅能依據不同的需求設計具有高速、高解析度或是低功率消耗的類比數位轉換器。
本論文即是採用一個新型的二階段比較架構,在犧牲一點速度的情況下,藉由開關切換在不同的參考電壓間做比較以達到低功率和低面積的需求,而在此架構下,比較器的使用量和編碼器的複雜度都大幅的減低。在低功率和小面積的需求下,此架構提供了另外一種更好的選擇。
Recently, the growing development of the process and handheld wireless terminals cause the demand of speed and power more important. Flash analog-to-digital converter is undoubtedly the major choice for high speed application but areas and power consumption are doubled with each bit of increased resolution. Therefore, Flash ADC is not suitable to high-resolution application. Consequently, an analog-to-digital converter having high speed, low power and high resolution is many people’s objectives. In fact, we can only design a analog-to-digital converter which having high speed, low power or high resolution according to different demands.
In this thesis, we proposed a novel two-step comparison structure in case of sacrificing some speed. The power and areas are saved by efficiently switching between different voltage levels. In this structure, the consumption of comparators and the complexity of the encoders are also decreased greatly. This new architecture makes a better candidate for many applications where power and size are major factors.
Chapter 1.................................................1
1.1 Motivation............................................1
1.2 Thesis Organization...................................2

Chapter 2.................................................4
2.1 Basic Concepts........................................4
2.1.1 Introduction of A/D Converter...................4
2.1.2 Aliasing Effect.................................5
2.1.3 Ideal A/D Converter.............................6
2.1.4 Quantization Error..............................7
2.2 A/D Converter Specification...........................9
2.2.1 Static Specification...........................10
2.2.2 Dynamic Specification..........................13
2.3 Flash A/D Converter..................................14
2.4 Bubble Effect........................................15
2.5 Encoding Scheme......................................17

Chapter 3................................................21
3.1 Introduction.........................................21
3.2 Flash ADC Architecture...............................21
3.3 New Power Saving Design Method for CMOS Flash ADC....23
3.4 A novel Bubble Tolerant Thermometer-to-Binary Encoder
for Flash A/D Converter..............................25
3.5 Proposed Two-Step ADC Architecture...................27
3.5.1 Comparator.....................................31
3.5.2 Encoder........................................33

Chapter 4................................................35
4.1 Simulation of Comparator.............................35
4.2 Simulation Results of Proposed ADC...................36
4.3 A/D Converter Testing................................38
4.3.1 FFT Testing....................................39
4.3.2 Histogram Testing..............................40
4.4 Comparison...........................................41

Chapter 5................................................43
[1] P. E. Allen and D.R Hoolberg, ‘CMOS Analog Circuit Design,’ New York: Oxford, 2002.

[2] D. A. Johns and K. Martin, ‘Analog Integrated Circuit Design,’ New York: Wiley 1997.

[3] M. Gustavsson, J. J. Wikner, and N. N. Tan, ‘CMOS Data Converter for Communications,’ Boston, MA: Kluwer Academic, 2002.

[4] E. Sall, M. Vesterbacka, K. O. Andersson. “A study of digital decoders in flash analog-to-digital converters,” in Proc.ISCAS ‘2004, vol1,May 2004, pp. 129-132.

[5] R. Kanan, F. Kaess, M. Declercq. “A 640 mW high accuracy 8-bit 1GHz flash ADC encoder,” in Proc. ISCAS ’99, vol. 2, June 1999, pp. 420-423.

[6] D. G. Knierim, “Error tolerant thermometer-to-binary encoder,” U.S. Patent no.4586025

[7] M. Choi, A. A. Abidi, “A 6-bit 1.3-Gsanple/s A/D converter in 0.35um CMOS,” IEEE solid-state Circuits, vol. 36, pp. 1847-1858, Dec.

[8] D. Lee, J. Yoo, K. Choi, and J. Ghaznavi. “Fat tree encoder design for untra-high speed flash A/D converter,” IEEE, 2002.

[9] A. Stojcevski, H.P. Le, J. Singh and A. Zayegh, “Flash ADC architecture”, IEE Electronics Letters, vol.39, no.6, pp. 501-502, Mar. 2003.

[10] T. Chia-Chun, H. Kai-Wei, H. Yuh-Shyan, L. Wen-Ta, and L. Trong-Yen. “New power saving design method for CMOS flash ADC,” The 47th IEEE International Midwest Symposium on Circuit and Systems, 2004.

[11] Yao-Jen Chuang, Hsin-Hung Ou, and Bin-Da Liu. “A novel bubble tolerant thermometer-to-binary encoder for flash A/D converter,” IEEE VLSI-TSA International Symposium, 2005.

[12] UYTTENIIOVE. K. and STEYAERT. M.S.J.: 'Speed-power-accuracy tradeoff in high-speed CMOS ADCs', IEEE Trans. Circuits Syst. 11, Analog Digit. Signal Process, 2002, 49, (4), pp. 280-287.

[13] STOJCCVSKI. A., SINGH. J. and ZAYEGH. A.: 'Modified flash ADC architecture with reduced power and complexity'. Proc. 4th Int. Conf. on Modeling and Simulation, MS'02, Melbourne, Australia, 2002, pp. 169-173

[14] Shih-Chang Hsia and Wen-Ching Lee.: 'A New 6-bit Flash A/D Converter using Novel Two-Step Structure,' IEEE Design and Diagnostics of Electronic Circuits and systems, 2006.

[15] R. Jacob Baker, ‘CMOS Circuit Design, Layout, and Simulation,’ IEEE Press Series on Microelectronic Systems, Stuart K. Tewksbury and Joe E. Brewer, series editors.

[16] Mark Burns and Gordon W. Roberts, ‘A Introduction to Mixed-Signal IC and Measurement,’ New York: Oxford, 2001.

[17] C. W. Hsu and T.H. Kuo, “ 6-bit 500MHz flash A/D converter with new design techniques”, IEEE proc. Circuits Devices Syst., vol.150, no. 5, pp. 460-464. 2003.

[18] Bang-Sup Song; Rankers, P.L.; Gillig, S.F., “A 1-V 6-bit 50MSamples/s current-interpolating CMOS ADC”, IEEE Journal of Solid-State Circuits, Vol. 35, no. 4, pp. 647-651, Apr., 2000.
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