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研究生:陳嘉斌
研究生(外文):Jia-Bin Chen
論文名稱:交錯式SEPIC功因修正器之分析與設計
論文名稱(外文):Analysis and Design of Interleaved SEPIC AC-DC Converters
指導教授:梁從主林瑞禮
指導教授(外文):Tsorng-Juu LiangRay-Lee Lin
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:75
中文關鍵詞:功因修正器交錯式控制
外文關鍵詞:PFCinterleaving control
相關次數:
  • 被引用被引用:9
  • 點閱點閱:474
  • 評分評分:
  • 下載下載:89
  • 收藏至我的研究室書目清單書目收藏:0
本文主旨係針對交錯式SEPIC功因修正器進行分析與設計。SEPIC是一種可昇降壓且輸入與輸出電壓為同極性的轉換器,故適合作為功率因數修正電路之用。另外,本文將第一台開關信號作時間移位,以此作為第二台開關信號,以達到交錯式控制,並透過雙台並聯達到高輸出功率需求。本論文首先說明基本型SEPIC轉換器電路架構,再探討交錯型SEPIC轉換器電路架構,分析其電路動作原理及電路參數設計。最後實作一400 W交錯式SEPIC功因修正器,以驗證本架構之可行性與電路特性。
In this thesis, interleaved SEPIC ac-dc converters are analyzed and designed. Since the SEPIC converter provides a positive-polarity regulated output voltage with respect to the common terminal of the input voltage, the SEPIC converter applied as a power factor corrector become feasible. Interleaving control is achieved by the time-shift between two SEPIC converter to supply more power to the load. The topologies of typical and interleaved SEPIC are discussed, and the operating principles and design process are also studied in the thesis. Finally, a laboratory prototype of a 400 W interleaved SEPIC ac-dc converter is implemented to verify its feasibility and characteristics.
中文摘要 i
誌 謝 iii
目 錄 iv
圖 目 錄 vi
表 目 錄 ix
第一章 緒論 1
1-1研究動機與背景 1
1-2研究方法與系統描述 2
1-3內容大綱 4
第二章 功因修正技術簡介 5
2-1功因的定義 5
2-2被動式功因修正技術 6
2-3主動式功因修正技術 8
2-3-1 連續導通模式(Continuous conduction mode, CCM) 8
2-3-2 臨界導通模式(Boundary conduction mode, BCM) 10
2-3-3 非連續導通模式(Discontinuous conduction mode, DCM) 11
2-4相關交錯式功因修正技術 11
第三章 交錯式SEPIC功因修正器 15
3-1基本型SEPIC轉換器 15
3-1-1 SEPIC轉換器動作原理 15
3-1-2 SEPIC轉換器操作於臨界導通模式之條件 26
3-2交錯式SEPIC轉換器 28
第四章 交錯式SEPIC功因修正器設計與實驗結果 36
4-1電氣規格與元件參數設計 36
4-2功因修正控制電路–MC33262介紹 41
4-2-1 MC33262功能介紹 41
4-2-2 MC33262外部電路參數設計 45
4-3交錯控制電路 47
4-4交錯式SEPIC功因修正電路實驗波形 49
第五章 結論與未來展望 59
5-1結論 59
5-2未來展望 59
參考文獻 61
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