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研究生:楊凱程
研究生(外文):Kai-Chen Yang
論文名稱:新型分時多工現場可規劃邏輯陣列之排程演算法
論文名稱(外文):Schedule Algorithm for New Time-Multiplexed FPGA
指導教授:賴源泰
指導教授(外文):Yen-Tai Lai
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:59
中文關鍵詞:分時多工現場可規劃邏輯陣列
外文關鍵詞:TMFPGA
相關次數:
  • 被引用被引用:0
  • 點閱點閱:118
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  • 下載下載:10
  • 收藏至我的研究室書目清單書目收藏:0
動態可重組的現場可規劃邏輯陣列(DRFPGAs)進化的速度很快,而且在製程進步的同時越來越受到歡迎,因為它提供了一種高效能且具有彈性的超大型積體電路設計技術。而在這些動態可重組的現場可規劃邏輯陣列中,最廣為流傳的架構就是Xilinx的分時多工現場可規劃邏輯陣列(TMFPGA)。這個架構有一種潛在的能力可以透過分時共用邏輯的方式來提升邏輯的使用率,而且在可重組計算(RC)這個領域中,它已經成為了一個很活躍的研究。
在本論文中,我們以一個新型分時多工現場可規劃邏輯陣列架構(New TMFPGA)除了解決傳統的分時多工現場可規劃邏輯陣列的優先次序限制(Precedence Constraint)問題外,不僅可以增加傳統分時多工現場可規劃邏輯陣列的彈性,而且還可以改善傳統分時多工現場可規劃邏輯陣列的效率,並改正了傳統架構上執行電路的延遲問題。。而在本論文中,我們針對這個新式分時多工現場可規劃邏輯陣列提出了一個創新的電路切割演算法(Circuit Partitioning Algorithm),在最大通訊成本不改變下,使得最大執行時間縮短,如此可使得電路總執行時間能減少。最後,實驗的結果證實了我們所使用的演算法是相當有效的。
Dynamically Reconfigurable FPGAs (DRFPGAs) are evolving rapidly, and they are more and more popular under proceed process, because they offer flexibility and high performance for the VLSI design technology. Among these DRFPGAs, the most popular architecture is the Xilinx Time-Multiplexed FPGA (TMFPGA). This architecture has a potential to improve logic utilization by time-sharing logic dramatically, and have become an active research for reconfigurable computing (RC).
In this thesis, we use a new TMFPGA (nTMFPGA) architecture to solve the precedence constraint problem of the traditional TMFPGA. This nTMFPGA not only increases the flexibility and improves the efficiency of the traditional TMFPGA but also improve the execution time delay problem with the traditional TMFPGA but also correct the function delay problem with the traditional TMFPGA.. In this thesis, we also propose a novel circuit partitioning algorithms for this nTMFPGA architecture to minimize the delay costs without increase the communication costs. Finally, the experimental results demonstrate the effectiveness of our approach.
CHAPTER 1 Introduction 1
1.1 BACKGROUND 1
1.2 STATIC RC AND DYNAMIC RC 3
1.3 TIME-MULTIPLEXED FPGA 4
1.4 THESIS ORGANIZATION 7
CHAPTER 2 Circuit Partitioning Problem 8
2.1 SPATIAL AND TEMPORAL PARTITIONING 8
2.2 CIRCUIT PARTITIONING FOR TIME-MULTIPLEXED FPGA 11
2.3 NODE MODELING 12
2.4 TRADITIONAL PRECEDENCE CONSTRAINTS 14
2.5 NEW TMFPGA AND NEW PRECEDENCE CONSTRAINTS 17
2.6 PREVIOUS WORKS FOR CIRCUIT PARTITION ALGORITHM 22
CHAPTER 3 Circuit Partitioning Algorithm 24
3.1 COSTS OF NEW TMFPGA 24
3.2 DEFINITION AND PROBLEM FORMULATION 25
3.3 DESIGN FLOW 28
3.4 LIST SCHEDULING 31
3.5 CONSTRUCTION OF A DIRECTED GRAPH 43
3.6 MINIMAL DELAY COSTS 46
CHAPTER 4 Experimental Results 52
4.1 EXPERIMENTAL FLOW 52
4.2 RESULTS AND DISCUSSION 53
CHAPTER 5 Conculsions 57
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[18]Xilinx, The Programmable Logic Data Book, 1996.
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