隨著CMOS元件尺寸持續縮微化，閘極氧化層厚度亦須隨之降低，以提高閘極對通道區內少數載子的控制能力。當製程技術進入45 nm世代以下時，所需要閘極氧化層等效厚度將小於或等於1.1 nm，此條件的氧化層等效厚度將造成閘極漏電流急劇增加，而影響元件的行為。事實上，過大的閘極漏電流將使得元件微縮進程中斷。在此情況下，高介電係數(high-κ)材料乃成為發展新世代CMOS製程技術，不可或缺的一環。
本論文將專注於以二氧化矽的界面層加上high-κ材料所形成之閘極堆疊介電層結構；並以一種量子機制的理論來探討此新型的閘極介電層其在低電場作用下可能引發閘極直接漏電流大小。由於電子的穿隧效應遠大於電洞，因而本論文將以p型基底的NMOS元件作用於反轉模式為主要的探討模型；另外在高品質的製程條件下，我們將假設界面陷阱的電荷可忽略不計入。吾人推導之量子模型考慮了四個重要的物理條件:一、反轉層內之量子機制的載子總電荷密度；二、反轉層量子機制的載子電荷之平均位移深度；三、反轉層載子的碰撞頻率；四、量子波函數穿隧機率。本論文依據的是一種分析的計算理論，在形成高品質的SiO2/high-κ介電質的閘極絕緣層，且元件作用於低電壓時，直接穿隧電流將會是閘極漏電流的主宰機制，利用量子機制來求得反轉層的電荷密度，並且根據修正的WKB近似法來求電子的穿隧機率，以及推算界面附近的電子碰撞頻率，然後利用電腦程式計算的有效模型，來得出P型基底的MOS元件反轉層時的直接穿隧電流﹙通過SiO2 & high-κ材料的介電層﹚此模式可以比較不同的SiO2界面厚度；不同high-κ介電係數因不同的阻障層高度的直接穿隧電流。例如在EOT等於1.5 nm時，使用界面層SiO2厚度等於0.7 nm，加上high-κ(HfO2 κ ~25，厚度4.8 nm)經由本論文模型可計算p型Si基板在反轉模式下的直接穿隧電流，較使用純粹SiO2厚度1.5 nm結構約低104~105之數量級。另外本論文的模擬結果與本實驗室的實際的數據，以及其它文獻的實作結果作比較，其閘極漏電流誤差只有101數量級以內，驗證出本論文理論模擬的準確性。
本論文的模型亦可比較相同的等效EOT條件的閘極介電層，不同的閘極堆疊介電層結構在不同的閘極電壓作用所可能引發的閘極直接穿隧漏電流大小；也可用來比較在相同的二氧化矽界面層厚度條件下，使用不同的high-κ材料形成相同EOT條件的閘極堆疊介電層，在不同的閘極電壓作用下所可能引發的閘極直接穿隧漏電流大小。經由本論文的模型，能快速獲得模擬的數據，如進而從中取出適合的機構，將可促使元件與製程的進步與改善。本論文模型不用繁冗的計算，且方程式的推導也很清晰讓人不至於迷失，如能歸納成為可輸入變數的應用軟體，將可造福科學界。

The continuous CMOS scaling has resulted in a continuous improving of the speed, power consumption, packing density and performance of integrated circuits. As the process technology becomes attractive for the 45 nm node and beyond, the equivalent oxide thickness (EOT) of the gate dielectrics oxide layer will be down to 1.1 nm or even thinner. It is quite obvious that the gate leakage current will be higher and CMOS circuit will fail, using the SiO2 in next process generation. Various insulators with high-permittivity (high-κ) have been proposed and investigated to serve as alternative to SiO2 toward CMOS technology of next generation.
In this study, we present a computationally efficient model to calculate the direct tunneling current from an inverted p-type (100) Si substrate through interfacial SiO2 and high-κ gate stacks. Four main physical conditions were considering : the total inversion layer charge density, the average inversion charge centroid thickness, the electron impact frequency on the interface, and the carriers tunneling probability. This model consists of quantum mechanical calculations for the inversion layer charge density and a modified WKB approximation for the transmission probability. The modeled direct tunneling currents agree well with a self-consistent model and experiment data, suggestion that the direct tunneling current is main domination of the gate leakage current in the low electrical field condition. For the same effective oxide thickness (EOT) of 1.5 nm, the direct tunneling current of a HfO2 high-κ dielectric (4.8 nm, κ ~25) overlaying a 0.7 nm thermal oxide is reduced about 4~5 order magnitude compared with a pure SiO2 film of the same EOT at low gate voltage. The effects of interfacial oxide thickness, dielectric constant and barrier height on the direct tunneling current have also been studied as a function of gate voltage.

論文合格證明(中文) I
論文合格證明(英文) II
中文摘要 III
英文摘要 V
誌 謝 VII
目錄 1
表目錄 4
圖目錄 5
第一章 緒論 8
1.1 MOS場效電晶體之發展 8
1.2 先進MOS場效電晶體之挑戰 9
1.3 研究動機 13
第二章 MOS場效電晶體與量子化效應之基礎理論 19
2.1 MOS場效電晶體基礎理論 19
2.1.1 MOS電容 19
2.1.2 MOS場效電晶體元件特性 21
2.1.3 基本的MOSFET操作 23
2.2 MOS元件量子機制的理論探討 25
2.2.1 量子的基本概念 25
2.2.2 量子的次能階與穿隧效應 26
2.2.3 MOS元件的量子機制 28
2.3 WKB近似法則的推導 29
第三章 量子機制穿隧電流模型建立 39
3.1 空乏層與反轉層之總載子密度 39
3.2 載子的碰撞頻率 42
3.3 量子機制的載子穿隧機率 43
3.4 閘極直接穿隧電流模型 45
第四章 結果與討論 58
4.1 模型與自洽結果之比較 58
4.2 SiO2與HfO2材料閘極直接漏電流之比較 59
4.3 不同high-κ材料的閘極直接漏電流之比較 60
4.4 模型與實驗數據之比較 61
第五章 結論與未來研究方向 72
5.1 結論 72
5.2 未來研究方向 74
參考文獻 75
自述 81

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