本論文主要著重在設計開發一個應用於超寬頻頻率合成器中的四相位除三架構；在這電路當中，我們整合了三個部分：（1）. 1,584MHZ的QVCO、（2）.單邊側頻帶（Single-Side Band） 的混頻器，以及（3）.除二電路 。上述三個電路將以米勒架構的型式建構出一個除3電路。
在這個米勒除頻器中，考量到之後量測時的便利性，故將一個四相位之震盪器整合在內，並藉著震盪器所提供的震盪訊號提供給混頻器應用；而在混頻器的設計中，為了有效降低功率的消耗以及濾出我們所需的頻帶，故我們使用LC-tank的方式去取代電阻。至於除二電路方面，在相當多種類的除2電路架構中，我們選取了差動式的組態，其原因不外乎於它天生上可得IQ四相位之輸出；但藉由主僕式D型正反器所實現的傳統靜態（static）除頻器，其操作電壓往往至少需要1.5伏特以上！這明顯不符合於本論文中低電壓除頻器的訴求；故在本論文中，我們藉由改變電晶體的配置方式，來達到壓低操作電壓的目的。
除此之外，有別於現今大多數除3電路架構，我們的電路其直流電壓（V ）操作於相當低的1.2伏特，以求壓低耗損功率。而如同我們所知，若欲在超寬頻多頻帶正交頻率分頻多工的系統中產生完整的14個次頻帶載波頻率訊號，除了除三電路是必需的之外，還需要有一個四相位之訊號，以提供給單邊側頻帶（single-sideband）混頻器產生相加或相減性的頻率合成。但由於一般數位式除三電路的除頻特質，其輸出訊號之振幅週期的Duty-Cycle不易為50％。而非50％之脈波寬的頻率若經過混頻器將產生許多諧波（harmonics），此舉將會使接收機之靈敏度大幅退化。由上所述，可知能夠產生四相位且振幅週期為50％的除3電路的重要性。由於在超寬頻頻率合成器中相鄰的兩個次頻帶其載波距離皆為528MHz，且其所需應用之訊號為四相位。故本論文規劃的除三電路將提供一個528MHz、四相位的輸出結果。
本論文主要貢獻如下：我們使用米勒架構的形式建構出一個除三電路，它不但可產生四相位的訊號輸出，且振幅週期亦達50％，使其可應用於超寬頻頻率合成器電路架構。此外，它的操作電壓更可壓低至1.2伏特以下，可充分地節省消耗功率。

The paper mainly presents the design of a quadrature divide-by-3 structure which can apply to UWB radio frequency synthesizer. We embrace three block in this circuit：（1）. 1.584 GHz QVCO, （2）. Low-voltage quadrature mixer, and（3）. Divide-by-2 circuit. The above 3 blocks will construct a divide-by-3 circuit by Miller type.
In this Miller divider, considering the convenience while measurement, we integrate a QVCO into this divider. By using the signal generated by QVCO apply to Mixer; And then, in order to reduce power consumption and peak the wanted frequency-band, we use the LC-tank to substitute for resistance. As for the divide-by-2 circuit, in various category of it, we choose the differential-type for the reason of it can natural get the qudrature output. But the conventional static divider which employed by the master-slave flip-flop usually need the operating voltage above 1.5V. It obviously not conform the “Low-Voltage Divider” request in this paper. So, we change the position of transistors to achieve the purpose of lower the operating voltage in our paper.
Furthermore, different from most nowadays divide-by-3 structures, the Vdd of our circuit can operate at a quite low voltage, it can save the power consuming very well. As we know, in order to generate 14 sub-band carrier frequency signal in Multi-band orthogonal frequency-division multiplexing （MB-OFDM）UWB system, expect for a divide-by-3 circuit, we also need a quadrature signal, which can provide to the single-sideband （SSB）mixer to generate adding or subtracting frequency synthesizing. But owing to the general dividing-frequency quality of the digital divide-by-3 circuits, it’s duty cycle of the output signal not facile to be 50%; If the frequency not having 50% pulse width passes through the mixer, it will be generating many harmonics and making the sensitivity produce a huge degeneration of the receiver. From the above, we can know the importance of the divide-by-3 circuits which can generate quadrature signal and the duty cycle is 50%. Because in the UWB frequency synthesizer, the sub-band which adjacent to each other is spaced at intervals of 528 MHZ, and the quadrature signal must be applied. So, the divide-by-3 circuit in our paper will supply a 528MHZ and quadrature output signal.
The mainly contributions of this paper are: We use the Miller type to construct a divide-by-3
circuit, it not also can generate a quadrature output, but also have a 50% duty cycle. So, it can be applied to the UWB frequency synthesizer. Furthermore, the operating voltage of this divider can lower to 1.2V, which can effectively reduce the power consumption.

Chinese Abstract I
English Abstract III
Acknowledgement V
List of Tables VIII
List of Figures IX


Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 3
1.3 Thesis Organization 5

Chapter 2 The Miller Divider 6
2.1 Architecture / Introduction of the integration circuit 6
2.2 Oscillator 8
2.2.1 Theory 8
2.2.2 Phase noise & Q of an Oscillator 14
2.2.3 The explain of negative resistance 18
2.3 Mixer 21
2.3.1 Theory 21
2.3.2 Characteristic of Mixer 22
2.3.2.1 Nonlinear and harmonic Effects 22
2.3.2.2 LO signal self-mixing & DC-offset 23
2.3.2.3 Considered Performance Parameter 25
2.3.3 Passive & Active Architecture 33
2.4 Divider 42
2.4.1 Theory 42
2.4.2 Major Topologies of Frequency Divider 43
Chapter 3 Design & Simulation 50
3.1 Design Flow 50
3.1.1 The background 50
3.1.2 Quadrature VCO 52
3.1.3 Mixer 63
3.1.4 Divide-by-2 circuit 70
3.2 Post-Simulation Results 75
3.2.1 QVCO Simulated Results 76
3.2.2 Mixer Simulated Results 78
3.2.3 Divide-by-2 Circuit Simulated Results 81
3.2.4 Integration Circuit Simulated Results 84

Chapter 4 Measurement Results 88
4.1 Measurement Consideration 88
4.2 The Miller Divider Measurement 91
4.2.1 Transient response 91
4.2.2 Power Spectrum & Phase Noise of the Divider 93
4.2.3 Performance 97

Chapter 5 99
5.1 Conclusions 99
5.2 Future Work 101

References 102

[1] Kazimier Siwiak,Debra Mckeown “Ultra-Wideband Radio Technology”, John wiley
[2] A.Batra et al.,”Multi-band OFDM physical layer proposal for IEEE 802.15 Task Group 3a,”IEEE, Piscataway, NJ, IEEE P802.15-03/268r2, Nov. 2003
[3] C. Mishra et a., “Frequency planning and synthesizer architectures for multiband OFDM UWB radios,” IEEE Trans. on Microwave Theory and Techniques. Vol. 53, issue 12, pp. 3744-3756, 2005.
[4] C.-F. Liang, S.-I. Liu, Y.-H. Chen, T.-Y. Yang, and G.-K. Ma, “A 14-band frequency synthesizer for MB-OFDM UWB application,” in the Digest of Technical Papers, IEEE 2006 International Solid-State Circuit Conference, pp.126-127, 2006.
[5] Bo Sun, “Divide-by-three circuit,” US patent, patent no. 6,389,095. (May 14,2002)
[6] Chien-chih Lin, Chorng-Kuang Wang, “A Regenerative Semi-Dynamic Frequency
Divider for Mode-1 MB-OFDM UWB Hopping Carrier Generation,” in the Digest of Technical Papers, 2005 IEEE International Solid-State Circuit Conference, pp.206-207, Feb. 2005.
[7] R.L. Miller, “Fractional-Frequency Generators Utilizing Regenerative modulation,” Proc. Inst. Radio Eng., vol. 27, no. 7, pp. 446-456, July,1939
[8] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”
[9] F. Herze1,et al., “Phase Noise in a Differential CMOS Voltage-Controlled Oscillator for RF Applications,” IEEE IPransactions on Circuits and Systems-II: Analog and Digital Signal
Processzng, vol. 47, no. 1, pp. 11-15, Jan. 2000.
[10] Behzad Razavi, “RF microelectronics”.
[11] Lin Jia, Jian-Guo Ma, Senior Member, IEEE, Kiat Seng Yeo, and Manh Anh Do, “9.3-10.4-GHz-Band Cross-coupled Complementary Oscillator With Low Phase-Noise Performance,” IEEE Transactions on Microwave Theory and Techniques, vol.52, No. 4, April 2004.
[12] A. Hajimiri and T. H. Lee, The Design of Low Noise Oscillators. Boston, MA: Kluwer, 1999.
[13] Jannesari, A.; Kamarei, M., “Design of a Low Voltage Low-Phase-Noise Complementary CMOS VCO,” Integrated Circuits, 2007. ISIC '07. International Symposium on 26-28 Sept. 2007 Page(s):426 – 429.
[14] D. Ham and A. Hajimiri, “Concepts and methods in optimization of integrated LC VCOs,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 896–909, Jun. 2001.
[15] P. Andreani, “Very low phase noise RF quadrature oscillator architecture,” Electron. Lett., vol. 37, pp. 902–903, Jul. 2001.
[16] P. J. Sulivan, B. A. Xavier, and W. H. Ku, “Low voltage performance of a microwave CMOS Gilbert cell mixer,” Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA; Solid-State Circuits, IEEE Journal of Volume: 32, Issue:7 on page(s): 1151-1155, Publication Date: Jul 1997
[17] O. Mitrea, C. Popa, A.M. Manolescu, and M. Glesner, “ A linearization technique for radio frequency CMOS Gilbert-type mixers,” Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on, Volume:3, On page(s): 1086- 1089 Vol.3, 14-17 Dec. 2003
[18] Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits,” Cambridge University Publishing,1998.
[19] Keng Leong Fong and R.G. Meyer, “Monolithic RF active mixer design,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on see also Circuits and Systems II: Express Briefs, IEEE Transactions on Volume 46, Issue 3, March 1999 Page(s):231-239.
[20] M.J. Gingell, “Single sideband modulation using sequence asymmetric polyphase networks,” Electrical Commun., Vol. 48, pp.21-25, 1973
[21] J.Park, C.-HO Lee, B.-S. Kim, and J. Laskar, “Design and Analysis of Low Flicker-Noise CMOS Mixers for Direct-Conversion Receivers,” Microwave Theory and Techniques, IEEE Transactions on, Volume:54, Issue:12, Part 2, on page(s): 4372-4380, Dec. 2006
[22] C.D. Hull, Joo Leong Tham, and R. R. Chu, “ A direct-conversion receiver for 900 MHz (ISM band) spread-spectrum digital cordless telephone,” Solid-State Circuits, IEEE Journal of Volume 31, Issue 12, Dec. 1996, Page(s): 1955-1963
[24] H. Darabi and A. A. Abidi, “Noise in RF-CMOS mixers: a simple physical model,” Solid-State Circuits, IEEE Journal of Volume: 35, Issue: 1, on page(s): 15-25, Publication Date: Jan 2000
[25] M.Bao, H. Jacobsson, L.Aspemyr, G.Carchon, and Xiao Sun., “A 9-31-GHz Subharmonic Passive mixer in 90-nm CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 41 , NO. 10, October 2006.
[26] Tae Wook Kim, Bonkee Kim, and Kwyro Lee, “Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors”, Solid-State Circuits, IEEE Journal of Volume 39, Issue 1, Jan. 2004 page(s): 223-229.
[27] C.Yu and J.S. Yuan, “Linearity and power optimization of a microwave CMOS Gilbert cell mixer,” Electron Devices for Microwave and Optoelectronic Applications, 2003, EDMO 2003, The 11th IEEE International Symposium on, on page(s): 234-239, 17-18 Nov.2003
[28] Chuanzhao Yu, J.S. Yuan, and Hong Yang, “ MOSFET linearity performance degradation subject to drain and gate voltage stress,” Device and Materials Reliability, IEEE Transactions on, Volume: 4, Issue: 4, on page(s):681-689, Dec. 2004
[29] I. Rovira, P. Sivonen, S. Rintamaki, and M. Honkanen, “Highly linear TX ID-chip for multicarrier GSM 900 and 1800 base station,” Circuits and Systems, 2001., The 2001 IEEE International Symposium on Volume:4, On page(s): 762-765 vol. 4, 6-9 May 2001
[30] B. Gilbert, “A Precise Four-Quadrant Multiplier with Subnanosecond Response,” IEEE Journal of Solid-State Circuits, Vol SG3, pp. 365-373, December 1968.
[31] H.M. Tuncer, F. Udrea, and G. A. J. Amaratunga, “A 5-GHz low power 0.18/splmu/m CMOS Gilbert cell mixer.” Semiconductor Conference, 2004. CAS 2004 Proceedings. 2004 International, Volume:1 , On page(s):-164, 4-6 Oct.2004
[32] 顏培仁，吳明瑞，呂明峰 “數位邏輯設計(digital design),” 滄海書局
[33] R.L. Miller “Fractional-frequency generators utilizing regenerative modulation,” Proc. Inst. Radio Eng, Vol.27, pp.446-456, Jul.1939
[34] Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S. –L. Jang, J.-F. Lee, and M.-H. Juang, “A Wide Locking Range and Low Voltage CMOS Direct Injection-Locked Frequency Divider,” IEEE Microwave and wireless components letters, Vol. 16, No. 5, May 2006
[35] Tiebout, M , “A CMOS Direct Injection-Locked Oscillator Topology as High-Frequency, Low-Power Frequency Divider,” Solid-State Circuits, IEEE Journal of Volume 39, Issue 7, July 2004 Page(s):1170-1174
[36] Yuan,J.; Svensson, C, “High-Speed CMOS Circuit Technique,” Solid-State Circuits, IEEE Journal of Volume 24, Issue 1, Feb. 1989 Page(s):62-70
[37] J. Navarro Soares, Jr., and W. A. N. Van Noije, “A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC),” IEEE Journal of Solid-State Circuits, Vol.34, No. 1, January 1999 Page(s):97-102
[38] X. P. YU, M.A. DO, W.M. Lim, K. S. Yeo and J.G. Ma, “Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler,” IEEE Transactions on Microwave Theory and Techniques, Vol. 54, No. 11, November 2006 Page(s):3828-3835
[39] S.Verma, H.R. Rategh and T. H. Lee, “A Unified Model for Injection-Locked Frequency Dividers,” IEEE Journal of Solid-State Circuits, Vol. 38, No .6, June 2003 Page(s):1015-1027
[40] J.Harvey and R. Harjani, “Analysis and Design of an Integrated Quadrature Mixer with Improved Noise, Gain, and Image Rejection,” Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on 6-9 May 2001 On page(s): 786 - 789 vol. 4
[41] F. Maloberti and M. Signorelli, “Quadrature Waveform Generator with Enhanced Performances,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 56-57, 1998
[42] Nakaska, J.K.; Haslett, J.W, “An Integrated 6.2-11 GHz SiGe Inductorless Injection Locked Frequency Divider,” 2005 European Microwave Conference Wolume 1, 4-6 Oct. 2005 Page(s):4 pp.
[43] A. Rofougaran, J. Rael, M.Rofougaran, A. Abidi, “A 900 MHz CMOS LC-Oscillator with Quadrature Outputs,” ISSCC 1996, PP. 392-393, Feb. 1996
[44] L. Jia, J.Ma, K.Yeo, M. Anh Do., “9.3-10.4-GHz-Band Cross-Coupled Complementary Oscillator With Low Phase-Noise Performance,” IEEE Transactions on Microwave Theory and Techniques, Vol.52, No.4, April 2004 Page(s):1273-1278
[45] P. Andreani., “A Low-Phase-Noise Low-Phase-Error 1.8GHz Quadrature CMOS VCO,” ISSCC 2002, Session 17, Advanced RF Techniques, Volume 2, Feb 3-7, 2002 Page(s):228 – 229
[46] Jannesari, A.; Kamarei, M, “Design of a Low Voltage Low-Phase-Noise Complementary CMOS VCO,” Integrated Circuits, 2007. ISIC '07. International Symposium on Publication Date: 26-28 Sept. 2007 On page(s): 426 – 429
[47] Srinivasan R. D.Z.Turker Sang Wook Park Sanchez-Sinencio, E. “A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications,”
[48] Mei-Ling Y. Sheng. H. K, and Wan. R. L., “A Low-Voltage 5-GHz Quadrature Up-Conversion Mixer for Wireless Transmitter,” Communications, Circuits and Systems Proceedings, 2006 International Conference on June 2006 Volume: 4 On page(s): 2618 – 2622
[49] S.Y. Lee, M.F. Huang and C.J. Kuo, “Analysis and Implementation of a CMOS Even Harmonic Mixer With Current Reuse for Heterodyne/Direct Conversion Receives,” IEEE Transactions on Circuits and Systems –I: Regular Papers, Vol.52, NO.9, September 2005
[50] NacEachern, L.A. Manku, T. “A Charge-Injection Method for Gilbert Cell Biasing,” Electrical and Computer Engineering, 1998. IEEE Canadian Conference on 24-28 May 1998
Volume: 1 On page(s): 365 - 368 vol.1
[51] Jun-Chau Chien Liang-Hung Lu , “Ultra-Low-Voltage CMOS Static Frequency Divider,” Asian Solid-State Circuits Conference, 2005 Nov. On page(s): 209 - 212