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研究生:黃辰瑋
研究生(外文):Chen-Wei Huang
論文名稱:應用於超寬頻射頻頻率合成器之低電壓米勒除三電路
論文名稱(外文):Low-Voltage Miller Divide-by-three Circuit for UWB RF Synthesizers
指導教授:黃尊禧
指導教授(外文):Tzuen-Hsi Huang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:106
中文關鍵詞:超寬頻頻率合成器混頻器除二電路除三架構四相位之震盪器
外文關鍵詞:Low-voltage quadrature mixerdivide-by-3 structure584 GHz QVCOUWB frequency synthesizerDivide-by-2 circuit
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本論文主要著重在設計開發一個應用於超寬頻頻率合成器中的四相位除三架構;在這電路當中,我們整合了三個部分:(1). 1,584MHZ的QVCO、(2).單邊側頻帶(Single-Side Band) 的混頻器,以及(3).除二電路 。上述三個電路將以米勒架構的型式建構出一個除3電路。
在這個米勒除頻器中,考量到之後量測時的便利性,故將一個四相位之震盪器整合在內,並藉著震盪器所提供的震盪訊號提供給混頻器應用;而在混頻器的設計中,為了有效降低功率的消耗以及濾出我們所需的頻帶,故我們使用LC-tank的方式去取代電阻。至於除二電路方面,在相當多種類的除2電路架構中,我們選取了差動式的組態,其原因不外乎於它天生上可得IQ四相位之輸出;但藉由主僕式D型正反器所實現的傳統靜態(static)除頻器,其操作電壓往往至少需要1.5伏特以上!這明顯不符合於本論文中低電壓除頻器的訴求;故在本論文中,我們藉由改變電晶體的配置方式,來達到壓低操作電壓的目的。
除此之外,有別於現今大多數除3電路架構,我們的電路其直流電壓(V )操作於相當低的1.2伏特,以求壓低耗損功率。而如同我們所知,若欲在超寬頻多頻帶正交頻率分頻多工的系統中產生完整的14個次頻帶載波頻率訊號,除了除三電路是必需的之外,還需要有一個四相位之訊號,以提供給單邊側頻帶(single-sideband)混頻器產生相加或相減性的頻率合成。但由於一般數位式除三電路的除頻特質,其輸出訊號之振幅週期的Duty-Cycle不易為50%。而非50%之脈波寬的頻率若經過混頻器將產生許多諧波(harmonics),此舉將會使接收機之靈敏度大幅退化。由上所述,可知能夠產生四相位且振幅週期為50%的除3電路的重要性。由於在超寬頻頻率合成器中相鄰的兩個次頻帶其載波距離皆為528MHz,且其所需應用之訊號為四相位。故本論文規劃的除三電路將提供一個528MHz、四相位的輸出結果。
本論文主要貢獻如下:我們使用米勒架構的形式建構出一個除三電路,它不但可產生四相位的訊號輸出,且振幅週期亦達50%,使其可應用於超寬頻頻率合成器電路架構。此外,它的操作電壓更可壓低至1.2伏特以下,可充分地節省消耗功率。
The paper mainly presents the design of a quadrature divide-by-3 structure which can apply to UWB radio frequency synthesizer. We embrace three block in this circuit:(1). 1.584 GHz QVCO, (2). Low-voltage quadrature mixer, and(3). Divide-by-2 circuit. The above 3 blocks will construct a divide-by-3 circuit by Miller type.
In this Miller divider, considering the convenience while measurement, we integrate a QVCO into this divider. By using the signal generated by QVCO apply to Mixer; And then, in order to reduce power consumption and peak the wanted frequency-band, we use the LC-tank to substitute for resistance. As for the divide-by-2 circuit, in various category of it, we choose the differential-type for the reason of it can natural get the qudrature output. But the conventional static divider which employed by the master-slave flip-flop usually need the operating voltage above 1.5V. It obviously not conform the “Low-Voltage Divider” request in this paper. So, we change the position of transistors to achieve the purpose of lower the operating voltage in our paper.
Furthermore, different from most nowadays divide-by-3 structures, the Vdd of our circuit can operate at a quite low voltage, it can save the power consuming very well. As we know, in order to generate 14 sub-band carrier frequency signal in Multi-band orthogonal frequency-division multiplexing (MB-OFDM)UWB system, expect for a divide-by-3 circuit, we also need a quadrature signal, which can provide to the single-sideband (SSB)mixer to generate adding or subtracting frequency synthesizing. But owing to the general dividing-frequency quality of the digital divide-by-3 circuits, it’s duty cycle of the output signal not facile to be 50%; If the frequency not having 50% pulse width passes through the mixer, it will be generating many harmonics and making the sensitivity produce a huge degeneration of the receiver. From the above, we can know the importance of the divide-by-3 circuits which can generate quadrature signal and the duty cycle is 50%. Because in the UWB frequency synthesizer, the sub-band which adjacent to each other is spaced at intervals of 528 MHZ, and the quadrature signal must be applied. So, the divide-by-3 circuit in our paper will supply a 528MHZ and quadrature output signal.
The mainly contributions of this paper are: We use the Miller type to construct a divide-by-3
circuit, it not also can generate a quadrature output, but also have a 50% duty cycle. So, it can be applied to the UWB frequency synthesizer. Furthermore, the operating voltage of this divider can lower to 1.2V, which can effectively reduce the power consumption.
Chinese Abstract I
English Abstract III
Acknowledgement V
List of Tables VIII
List of Figures IX


Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 3
1.3 Thesis Organization 5

Chapter 2 The Miller Divider 6
2.1 Architecture / Introduction of the integration circuit 6
2.2 Oscillator 8
2.2.1 Theory 8
2.2.2 Phase noise & Q of an Oscillator 14
2.2.3 The explain of negative resistance 18
2.3 Mixer 21
2.3.1 Theory 21
2.3.2 Characteristic of Mixer 22
2.3.2.1 Nonlinear and harmonic Effects 22
2.3.2.2 LO signal self-mixing & DC-offset 23
2.3.2.3 Considered Performance Parameter 25
2.3.3 Passive & Active Architecture 33
2.4 Divider 42
2.4.1 Theory 42
2.4.2 Major Topologies of Frequency Divider 43
Chapter 3 Design & Simulation 50
3.1 Design Flow 50
3.1.1 The background 50
3.1.2 Quadrature VCO 52
3.1.3 Mixer 63
3.1.4 Divide-by-2 circuit 70
3.2 Post-Simulation Results 75
3.2.1 QVCO Simulated Results 76
3.2.2 Mixer Simulated Results 78
3.2.3 Divide-by-2 Circuit Simulated Results 81
3.2.4 Integration Circuit Simulated Results 84

Chapter 4 Measurement Results 88
4.1 Measurement Consideration 88
4.2 The Miller Divider Measurement 91
4.2.1 Transient response 91
4.2.2 Power Spectrum & Phase Noise of the Divider 93
4.2.3 Performance 97

Chapter 5 99
5.1 Conclusions 99
5.2 Future Work 101

References 102
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