隨著半導體製程的發展以及單晶片系統設計複雜度的提高，使用更高層級的設計方法以及快速的驗證都是未來的趨勢。因此電子系統層級的設計方法會在未來逐漸有著重要的地位。憑藉高速模擬的特性，系統設計者能以更快的方式在不同架構組態下的效能評估。藉由在電子系統層級作系統發展並且實現到較低層級，可以大幅縮減開發此產品所需的時間。除此之外，對一個系統而言，為了能確保內部的每一個元件能正常執行，發展一個對應的測試機制仍舊是一個很重要的議題。
在此篇論文裡，我們發展在電子系統層級的測試平台來提升模擬速度。對於反覆相同動作的元件，我們減少其動作的模擬次數來快速得到結果，並且分析此方法對模擬速度提升的程度。透過測試元件參數化，我們可以快速評估不同組態下的測試效能。藉著高速模擬以及快速架構重構的特性，設計者可以在短時間內針對不同單晶片系統來訂定適用的測試架構。實驗結果顯示，測試平台的模擬速度在電子系統層級比在暫存器傳輸層級下快六萬倍之多。此結果也強烈顯現出在電子系統層級下其模擬速度大幅提升。另一項實驗結果顯示出使用電子系統層級的測試平台，我們可以在高精準度下快速評估不同組態下的測試時間以及架構變更後的總面積。

With the development of semiconductor processing and increasing complexity of SoC design, designing in higher level and faster verification becomes a trend. Therefore, electronic system level (ESL) design methodology will be more and more important in the future. With the feature of high-speed simulation, system designers can evaluate the performance in different configurations of the architecture in a rapid way. Through developing system in ESL and implementing in lower level, it can decrease the time for product development. In addition, developing a corresponding test mechanism is still an important issue to assure the functionality of every component in a system.
In this thesis, in order to improve the simulation speed, we construct an ESL test platform. By reducing the times to repeat the same actions, the simulation time can be greatly decreased. Also with the parameterized test components, we can efficiently evaluate test efficiencies in different configurations. Through the high simulation speed and fast architecture reconfiguration, designers can determine suitable test architectures according to specified SoC requirements. Experimental results show that the simulation speed of test platform at ESL can be 60000 times faster than that at RTL. Another experimental results show that we can use ESL test platform to estimate the test time and areas of refined architectures with high accuracy.

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Overview 2
1.3 Organization 2
Chapter 2 Background 4
2.1 IEEE Standards 4
2.1.1 IEEE 1500 Standard 4
2.1.2 IEEE 1666 Standard 7
2.2 Overview of SoC Test Platform 9
2.2.1 Hardware Component 9
2.2.2 Software Components 11
2.2.3 Test Procedures 11
2.3 Transaction Level Model 13
2.3.1 Category of TL Modeling 13
2.3.2 Un-Timed Modeling 15
Chapter 3 Un-Timed Test Platform 19
3.1 Features 19
3.2 Processor 20
3.3 System Bus 21
3.4 Arbiter 22
3.5 Interrupt Service Routine 22
3.6 TAM Controller 23
3.6.1 Wrapper 25
3.6.2 Control Unit 26
3.6.3 Memory Access Unit 29
3.6.4 Shift Unit 29
3.6.5 TMS Generator 30
3.6.6 Comparator 32
3.7 TAP Controller 32
3.8 Virtual Scan Model 33
3.9 Test Bus 34
3.10 Automation Tool 35
3.10.1 Instruction Generator 35
3.10.2 Pattern Transformer 36
3.10.3 Test Bus Generator 37
Chapter 4 Exploration of Test Architecture 38
4.1 Conception 38
4.2 Parameter 40
4.2.1 TMS Generator Modeling with Parameter 41
4.2.2 Shift Buffer Modeling with Parameter 42
Chapter 5 Experimental Result 43
5.1 Experimental Environment 43
5.2 Simulation Time of CUT Testing 44
5.3 Analysis of Simulation Time 46
5.4 Experimental Results of Test Architecture Exploration 47
Chapter 6 Conclusions 50
References 51

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