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研究生:陳紹元
研究生(外文):Shao-Yuan Chen
論文名稱:具有即時監控核心電路與系統匯流排能力之低成本單晶片系統除錯平台
論文名稱(外文):A Low-Cost On-Chip SOC Debug Platform with On-Line Monitor Capability for System Bus and IP Cores
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:60
中文關鍵詞:分段擷取除錯
外文關鍵詞:debugtime division
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隨著半導體製程之演進,愈來愈多核心電路被整合進系統單晶片(System-on-a-chip),以軟體為基礎的模擬方式己經無法保證實際的晶片能正常運作。所以使用者常常浪費大量時間去除錯或驗證系統單晶片,為了有效節省除錯及驗證時間,使用者需要一套有系統的除錯方法。
在此篇論文裡,我們發展出一套具有除錯機制的系統單晶片除錯平台。此除錯平台包含了硬體及軟體設計,它支援在核心電路執行正常運算時,同時擷取系統匯流排或核心電路的輸入/輸出埠的資訊。另外,為了有效減少擷取的資料量,我們也發展了資料壓縮及分段擷取的技術來解決此問題。由於現今愈來愈多系統單晶片都整合了測試元件,所以我們重覆利用測試元件支援除錯的機制達到降低成本目的。此除錯平台也提供一個具有軟/硬體一起驗證的(co-verification)機制,此機制可以自動地比對擷取結果與預期結果是否有錯誤產生,可有效節省驗證時間。
最後,為了讓我們所發展除錯機制更人性化,一個以圖形介面為基礎的除錯軟體也被提出,使用者可利用此軟體快速將核心電路整合進我們所提出的系統單晶片除錯平台,此除錯軟體也提供互動式的介面讓使用者設定除錯參數並顯示除錯結果。
As the increasing complexity of IP cores integrated into a SoC, software-based simulation model cannot ensure that first silicon will work correctly. Debugging and verification for first silicon are often time-consuming. Therefore, designers need an efficient approach to catch design errors while debugging. In this thesis we propose debug platform contains hardware/software designs. Within the proposed debug platform, we develop a novel real-time system monitor, called the on-line trace. When intellectual property (IP) cores are under normal operation, the on-line trace mechanism can monitor and capture data simultaneously. To reduce trace data volume, we also develop a data compression with time division technique to reduce trace data size. Furthermore, we reuse original test components to reduce area overhead. A friendly graphic user interface is also provided to bring conveniences to designers for rapidly building a debug platform and analyzing trace data from the real chip.
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Overview 2
1.3 Organization 3
Chapter 2 Background & Previous Work 5
2.1 Background 5
2.1.1 Versatile Platform Baseboard with Logic Tile 5
2.1.2 AMBA Buses 6
2.1.3 IEEE 1500 Standard 8
2.1.4 SoC Test Platform 10
2.2 Previous Work 12
2.2.1 Microprocessor-based debugging 12
2.2.2 Platform-based debugging 13
Chapter 3 Overview of SOC Debug Platform and Procedure 18
3.1 Overall Architecture of SoC Debug Platform 18
3.2 Debug Procedure 20
Chapter 4 Implementation of SoC Debug Platform with On-line Trace Mechanism 22
4.1 Design of TAM Controller 22
4.1.1 Architecture of TAM Controller 23
4.1.2 Data Registers 25
4.2 Bus Monitor 28
4.2.1 Debug Flow of Bus Monitor 29
4.2.2 Architecture of Bus Monitor 30
4.2.3 Trace Data Reduction 32
4.3 Boundary Wrapper Monitor 35
4.3.1 Debug Flow of Boundary Wrapper Monitor 35
4.3.2 Architecture of Boundary Wrapper Monitor 36
4.4 On-chip Memory Architecture 38
Chapter 5 Experimental Results 40
5.1 Simulation Environment of Virtual Level 40
5.2 Synthesis Results and Simulation Results 42
Chapter 6 Hardware/Software Integration and Verification 47
6.1 HW/SW Integration Flow 47
6.2 Self-developed Graphic User Interface 49
6.2.1 On-line Trace Procedure 52
6.3 Experimental Results of Physical Level 53
Chapter 7 Conclusions 57
7.1 Conclusions 57
References 59
[1]M.C Hsieh and C.T. Huang, “An Embedded Infrastructure of Debug and Trace Interface for DSP Platform,”in Proc. DAC, pages 866-871, 2008.
[2]S. Tang and Q. Xu, “A Debug Probe for Concurrently Debugging Multiple Embedded Cores and Inter-Core Transactions in NoC-Based System,” IEEE ASPDAC, pages 416-421, 2008.
[3]B. Vermeulen, “Functional Debug Techniques for Embedded Systems,” IEEE Design & Test of Computers, pages 208-215, May 2008.
[4]Y.T. Lin, W.C. Shiue and I.J. Huang, “A Multi-resolution AHB Bus Tracer for Real-time Compression of Forward/Backward Traces In a Circular Buffer,” in Proc. DAC, pages 862-865, 2008.
[5]C.F. Kao, I.J. Huang and C.H. Lin, “An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration,” in Proc. DAC, pages 477-482, 2007.
[6]S. Tang and Q. Xu, “A Multi-Core Debug Platform for NoC-Based Systems,” in Proc. DATE, pages 1-6, 2007.
[7]W.C. Huang, C.Y. Chang and K.J. Lee, “Toward Automatic Synthesis of SoC Test Platform,” VLSI Design, Automation, and Test, pages 1-4, 2007.
[8]C.C. Yen, T. Lin, H. Lin, K. Yang, T. Liu and Y.C. Hsu, “Diagnosing Silicon Failures Based on Functional Test Patterns,” IEEE MTV, pages 94-98, 2006.
[9]P. Bernardi, M. Grosso, M. Rebaudengo and M.S. Reorda, “Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores,” IEEE MTV, pages 55-62, 2005.
[10]K.J. Lee, C.Y. Chu and Y.T. Hong, “An Embedded Processor Based SOC Test Platform,” Proc. Int’l Symp. on Circuits and Systems, pages 2983-2986, 2005.
[11]N. Stollon, R. Leaterman, B. Ableidinger and E. Edgar, “Multi-Core Embedded Debug for Structured ASIC System,” DesignCon 2004.
[12]I.J. Huang, C.F. Kao, H.M. Chen, C.N. Juan and T.A. Lu, “A Retargetable Embedded In-Circuit Emulation Module for Microprocessors,” IEEE Design & Test of Computers, pages 28-38, 2002.
[13]B. Vermeulen and S.K. Goel, “Design for Debug: Catching Design Errors in Digital Chips,” IEEE Design & Test of Computers, pages 35-43, 2002.
[14]Yu-Ting Hung and Kuen-Jong Lee, “An Embedded-Processor-Driven Platform for SOC Testing,” NCKU master thesis, 2002.
[15]P.C. Ching, Y.H. Cheng and M.H. Ko, “An in-Circuit Emulator for TMS320C25,” IEEE Trans. on education, VOL. 37, NO. 1, Feb. , pages 51-56, 1994.
[16]IEEE P1500 Standard for Embedded Core Test (SECT), http://grouper.ieee.org/groups/1500/.
[17]AMBA Specification, http://www.arm.com.
[18]Chipscope Pro Software and Core User Guide, Xilinx Inc., Oct. 2004.
[19]Versatile platform baseboard for ARM926EJ-S user guide Web Site, http://www.arm.com.
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