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研究生:楊得煒
研究生(外文):Der-Wei Yang
論文名稱:低功率及高面積效率之腓特比解碼器設計及其矽智產產生器
論文名稱(外文):Low-Power and Area-Efficient Viterbi Decoder Design and Its IP Generator
指導教授:謝明得謝明得引用關係
指導教授(外文):Ming-Der Shieh
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:55
中文關鍵詞:超大型積體電路矽智產產生器低功率設計腓特比解碼器
外文關鍵詞:IP generatorlow power designVLSIViterbi decoder
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迴旋碼及腓特比解碼器已被廣泛使用於各式數位通訊系統標準中,以得到較低的位元錯誤率進而提升系統的傳輸品質。然而在無線技術快速發展之下,針對不同應用之各式通訊協定即因應而生,因此在各個標準中對腓特比解碼器的規格需求也不盡相同,例如在短距離無線裝置之應用如超寬頻 (MB-OFDM) 上,通常需要極高的資料輸出率;對於手持裝置而言,低功率消耗則是電路設計的基本前提,為了能夠設計出符合各種標準且有效率的腓特比解碼器,並且縮短電路設計的時間,一有效率的腓特比解碼器之矽智產產生器將扮演著非常重要的角色。
主論文主要是探討腓特比解碼器在硬體實現上常遇到的兩個重要問題:如何降低存活路徑儲存單元的高功率消耗,以及當系統頻率高於電路之輸出率時,為節省面積而使用面積效率架構所造成的高連接線複雜度。除了針對這兩個主要的問題提出改良之架構外,並基於此架構建立一可參數化的電路並延伸為矽智產產生器。
Convolutional codes and Viterbi decoders (VDs) are widely applied to modern digital communication systems for reducing the overall bit error rate and improving the resulting performance. Rapid development in wireless techniques also results in the emergence of a variety of communication standards, each aiming at different applications. This in turn implies that different VD specifications might be needed in different communication standards. For example, a short-distance wireless communication such as the MB-OFDM UWB requires an ultimate high throughput rate, while portable devices demand low power consumption. As a result, an efficient VD IP generator would be required to shorten the design time and to take into account the effects of different VD specifications.
The primary challenges of VD designs are the large power consumption of storage elements such as those for the survivor memory management, and the high interconnect complexity in area-efficient architectures adopted when the system clock rate is faster than the required throughput rate. This thesis presents improved architectures to solve the two problems and then develop a parameterized IP generator based on proposed VD architectures.
Table Of Content iii
List Of Figures v
List Of Tables vii
Chapter 1 Introduction 1
1.1 Channel Coding 1
1.2 Motivation 2
1.3 Thesis Overview 3
Chapter 2 Viterbi Hardware Architecture 4
2.1 Viterbi Algorithm and Implementation 4
2.2 Branch Metric Unit (BMU) 9
2.3 Add Compare Select Unit (ACSU) 10
2.4 Survivor Memory Unit (SMU) 12
Chapter 3 Enhanced Architectures 15
3.1 Segmented Register Exchange Method 15
3.1.1 Segmented RE with TFU (m-level SRE) 17
3.1.2 Segmented conventional RE (bit-level SRE) 21
3.1.3 SRE with Scarce State Transition (SST) 23
3.2 Fixed Interconnections Area-Efficient ACSU 25
3.2.1 Conflict Free Memory Access 26
3.2.2 Extended In-place Scheduling 31
3.2.3 Local Memory with Pseudo Bank Architecture 34
3.3 Experimental Results 38
3.3.1 Experimental Results of SRE 38
3.3.2 Experimental Results of Fixed Interconnections ACSU 41
Chapter 4 Viterbi Decoder IP Generator 44
4.1 Specifications and Parameters 44
4.2 IP Generator Design 47
4.3 Verification Flow and Application Methods 49
Chapter 5 Conclusions and Future Work 52
5.1 Conclusions 52
5.2 Future Work 53
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