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研究生:賴榮來
研究生(外文):Rong-Lai Lai
論文名稱:利用廣大區域邊緣線平均與動態經歷偵測之動態適應解交錯器演算法及硬體設計
論文名稱(外文):Algorithm and VLSI Design of Motion Adaptive De-interlacer via Wide Range Edge Based Line Averaging
指導教授:李國君李國君引用關係
指導教授(外文):Gwo-Giun Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:96
語文別:英文
論文頁數:96
中文關鍵詞:動態適應性解交錯器
外文關鍵詞:intra-fieldde-interlacingmotion adaptive
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本論文提出一個動態適應性解交錯之演算法與硬體架構設計,動態適應性解交錯器的演算法能根據是否有移動來決定補點方法是使用時間軸上的資訊或空間上的資訊。在發表的解交錯演算法中主要由判斷與補點的方法所組成,發表的判斷方法由動態偵測、紋路偵測與明顯邊界的偵測所組成,其中動態偵測使用動態經歷與相對應區塊將能有效的判斷動態狀態,而對於空間方向的補點,我們可以依據補點位置內容資訊的不同使用紋路偵測與明顯邊界的偵測來選擇適當空間補點方法。在發表的補點方法主要由廣大區域邊緣線平均法、垂直方向濾波法與時間軸上圖平均法三者所構成,其中發表的廣大區域邊緣線平均法使用適應性可調變的搜尋視窗去評估邊界的方向,另外此方法也使用明顯邊界偵測和中間值濾波法分別改善在非明顯邊界區域的錯誤偵測和防止異常圖素的發生。
主要有兩個處理單元在發表的硬體架構中,第一個處理單元偵測區塊能輸出控制訊號來選擇補點的方法,另一個處理單元選擇適當的補點方法來輸出解交錯的處理結果,在發表的硬體架構利用UMC.18μm的製程規格來進行邏輯電路合成,操作的頻率為54百萬赫茲。
The goal of this thesis is to present a motion adaptive de-interlacing algorithm and its corresponding hardware implementation in light of its ability to determine inter-field or intra-field interpolation according to motion. The proposed de-interlacing algorithm consists of some detection methods such as motion detection, texture detection, and high frequency detection. Motion detection using motion history and the corresponding block can effectively detect the motion state. The appropriate spatial interpolation scheme using texture detection and high frequency detection can be selected according to different content data. The proposed interpolation methods are Wide Range Edge-based Line Average (WRELA), vertical filter, and field average. The proposed WRELA adaptively changes the search window to estimate the edge direction. In addition, WRELA also uses dominant edge detection and median filter to improve erroneous detection in a region with non-dominant directional edge and prevent the occurrence of bursting pixels, respectively.
There are two processing elements in the proposed hardware architecture. The first is the detection block which can output control signal to select the interpolation method. The other is the interpolation block which can output the de-interlacing processing result. The proposed architecture is synthesized with UMC.18 μm technique cell library. The operating speed is 54 MHz.
Abstract iii
Table of Contents v
List of Tables vii
List of Figures viii
Chapter 1 Introduction 1
1.1 Background 1
1.2 Organization of this Thesis 3
Chapter 2 De-interlacing Algorithms Overview 4
2.1 De-interlacing Problem Statement 4
2.2 Non-Motion Compensated Methods 7
2.2.1 Spatial Interpolation 7
2.2.2 Temporal Interpolation 14
2.2.3 Spatial-Temporal Interpolation 16
2.3 Motion Compensated Methods 20
Chapter 3 Motion-Adaptive De-interlacing 21
3.1 Motion Detection 21
3.1.1 Two-Field Motion Detection 22
3.1.2 Three-Field Motion Detection 24
3.1.3 Four-Field Motion Detection 25
3.1.4 Five-Field Motion Detection 26
3.1.5 Other Methods 28
3.2 Motion Fading 30
Chapter 4 Proposed Algorithm and Architecture 32
4.1 Proposed De-interlacing Algorithm 32
4.1.1 Detection Schemes 34
4.1.2 Interpolation Schemes 38
4.2 Architecture Design and Implementation 49
4.2.1 Design Specification 49
4.2.2 Architecture and Hardware Implementation 50
4.2.3 Memory Configurations 60
Chapter 5 Verification and Experimental Results 62
5.1 Verification Process 62
5.1.1 Individual Sub-Module Verification 62
5.1.2 Macro-Level Verification 64
5.1.3 ARM-Based System Verification 65
5.2 Experimental Results 68
5.2.1 Performance Evaluation Method 68
5.2.2 Simulations Results for proposed WRELA 69
5.2.3 Simulations Results for Proposed De-interlacing Algorithms 80
5.2.4 Implementation Results 87
Chapter 6 Conclusions and Future Work 89
6.1 Conclusions 89
6.2 Future Work 90
References 91
Appendix 95
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[16]S.F. Lin, Y.L. Chang, and L.G. Chen, “Motion Adaptive Interpolation with Horizontal Motion Detection for De-interlacing”, IEEE Transactions on Consumer Electronics, Vol. 49, No. 4, pp.1256-1265, November 2003.
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[24]Y. Shen, D. Zhang, Y, Zhang, and J. Li “Motion Adaptive Deinterlacing of Video Data with Texture Detection”, IEEE Transactions on Consumer Electronics, Vol. 52, No. 4, pp. 1403–1408, November 2006.
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[27]G.G. Lee, H.Y. Lin, M.J. Wang, R.L. Lai, C.W. Jhuo, “A High-Quality Spatial-Temporal Content-Adaptive Deinterlacing Algorithm”, IEEE International Symposium on Circuits and Systems, pp. 2594-2597, May 2008.
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