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研究生:郭信智
研究生(外文):Hsin-Chih Kuo
論文名稱:應用於60-GHzCMOS毫米波射頻接收機前端電路之研製
論文名稱(外文):Design of CMOS RFICs for 60-GHz Millimeter-Wave Wireless Receiver RF Front-End
指導教授:莊惠如莊惠如引用關係
指導教授(外文):Huey-ru Chuang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電腦與通信工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:107
中文關鍵詞:射頻接收機低雜訊放大器混頻器毫米波
外文關鍵詞:60 GHzMillimeter-wavereceiver front-endlow-noise amplifiermixer
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本論文研製60-GHz CMOS毫米波射頻接收機前端電路,使用標準TSMC CMOS 0.13 μm與TSMC CMOS 0.18 μm製程製作,量測皆採用on-wafer方式進行。論文主要分為兩部分,第一部分介紹IEEE 802.15.3c標準制定歷史以及毫米波相關研究背景,並收集目前發展較具完整性的系統進行說明,最後根據參考文獻估算60-GHz WPAN前端系統之鏈路預算。
第二部份為60-GHz CMOS毫米波射頻前端接收機之電路設計與量測結果。首先為低雜訊放大器的部份,以三級共源極放大器串接架構做為核心放大器並成功降低消耗功率。供應電壓VDD為1.2 V,整體的消耗功率為21.6 mW。57 – 64 GHz增益為5 – 7.6 dB,最佳增益值則出現在50 GHz為11.7 dB,最佳雜訊指數則為7.9 dB。混頻器實現了20-GHz CMOS 0.18-μm低電壓雙閘極混頻器以及60-GHz CMOS 0.13-μm毫米波雙閘極混頻器,利用雙閘極混頻器架構提升LO-RF隔離度,並利用一組LC串聯諧振,成功提昇LO-IF隔離度。雖然20-GHz CMOS低電壓雙閘極混頻器之IF緩衝放大器發生振盪,但混頻器核心功能正常,並經由量測結果得知,所設計之LC串聯諧振成功提昇整體隔離度,埠對埠隔離度皆大於20 dB。至於60-GHz CMOS毫米波雙閘極混頻器部分,設計時於中頻輸出端增加穩定電阻,避免振盪情形發生。量測結果顯示:轉換損耗為2.7 dB,單旁波雜訊指數為21.5 dB,總消耗功率為16.8 mW。最後則為60-GHz CMOS 0.13-μm毫米波射頻前端接收機之研製,承襲上述之架構組合而成,並將IF端輸設計為寬頻匹配,如此可符合不同系統規劃應用。量測結果顯示:RF在47 GHz時,其轉換增益最大值為12.7 dB,3-dB頻寬為4 GHz。雖然達13 GHz之頻漂,但仍證明了使用CMOS 0.13 μm製程實現60-GHz CMOS毫米波收發機電路之可行性。
This thesis presents the design on CMOS RFICs for 60-GHz millimeter-wave wireless receiver RF front-end. The RFICs are fabricated with TSMC CMOS 0.13 μm 1P8M and TSMC CMOS 0.18 μm 1P6M standard processes. In the first part of the thesis, we introduce the millimeter-wave for short-range high data-rate WPAN applications and a brief chronology of the 60-GHz standardization activity. The block diagrams and link budget of the 60-GHz WPAN system are also discussed.
The second part of this thesis presents the design and measurement of CMOS RFICs for 60-GHz millimeter-wave RF front-end. First of all, a three-stage cascaded common source LNA is presented. The LNA has demonstrated a gain of 11.7 dB and a minimum noise figure of 7.9 dB at 50 GHz. The total power consumption is 21.6 mW from a 1.2 V power supply. Compared to the other works using 0.13 μm CMOS, this work has shown that the LNA reduces power consumption successfully. In addition, a 20-GHz CMOS 0.18-μm low voltage dual-gate mixer and a 60-GHz CMOS 0.13-μm millimeter-wave dual-gate mixer are proposed. In order to improve port-to-port isolation, a LC series resonator is designed to bypass the LO signal. On other hand, the 60-GHz CMOS millimeter-wave dual-gate mixer has a conversion loss of 2.7 dB and a SSB NF of 21.5 dB. The total power consumption is 16.8 mW from a 1.2 V power supply. Reasonable agreements of the S-parameters and the conversion loss between simulation and measurement were obtained. Finally, a 60-GHz CMOS 0.13-μm millimeter-wave RF receiver front-end is presented. The measurement shows a maximum conversion gain of 12.7 dB at 47 GHz. The 3-dB bandwidth is 4 GHz. The receiver front-end draws 36.4 mA from a 1.2 V power supply. Although there is 13 GHz frequency offset between simulation and measurement, it is feasible to implement a 60-GHz RF receiver front-end using CMOS 0.13-μm process.
第一章 緒論 1
1.1 短距離無線通訊系統介紹 1
1.2 IEEE 802.15.3c標準制定歷史及毫米波研究背景 3
1.3 論文架構 8

第二章 60-GHz WPAN射頻前端系統簡介 9
2.1 60-GHz WPAN射頻前端系統方塊 9
2.1.1 60-GHz BiCMOS transceiver with 9 GHz IF 10
2.1.2 60-GHz CMOS heterodyne receiver with 20 GHz IF 11
2.1.3 5/60 GHz radio 13
2.1.4 實驗室完整規劃 14
2.2 60-GHz WPAN射頻前端系統鏈路預算 16
2.3 討論 22

第三章 60-GHz CMOS毫米波低雜訊放大器 23
3.1 CMOS毫米波低雜訊放大器介紹 23
3.2 電晶體雜訊來源、量化與雜訊指數 25
3.2.1 電晶體雜訊來源與量化 25
3.2.2 等效輸入雜訊溫度 29
3.3 CMOS毫米波低雜訊放大器設計流程 31
3.3.1 電路架構考量 31
3.3.2 共源極架構雜訊模型 32
3.3.3 電晶體尺寸選擇 33
3.3.4 輸入匹配網路設計 34
3.3.5 介質層等效介電係數驗證 38
3.3.6 完整電路設計流程與考量 41
3.4 V-band量測環境設定與注意事項(詳見附錄A) 43
3.4.1 V-band S-parameter與IP1dB之量測注意事項 43
3.4.2 V-band雙音測試之量測注意事項 44
3.4.3 V-band NF之量測注意事項 45
3.5 模擬與量測結果 46
3.5.1 60-GHz CMOS毫米波低雜訊放大器模擬結果 46
3.5.2 60-GHz CMOS毫米波低雜訊放大器量測結果 46
3.6 結果與討論 50

第四章 20-GHz及60-GHz CMOS雙閘極混頻器 53
4.1 混頻器原理與重要參數介紹 53
4.2 毫米波混頻器架構應用介紹 55
4.2.1 吉伯特混頻器(Gilbert mixer) 56
4.2.2 電阻性混頻器(resistive mixer) 57
4.2.3 單閘極混頻器(single-gate MOSFET mixer) 58
4.2.4 雙閘極混頻器(dual-gate MOSFET mixer) 59
4.3 20-GHz CMOS低電壓雙閘極混頻器 60
4.3.1 雙閘極混頻器偏壓點設計 60
4.3.2 電晶體尺寸選擇 62
4.3.3 LO匹配網路設計考量 66
4.3.4 LC串聯諧振設計考量 66
4.3.5 緩衝放大級 68
4.3.6 完整電路設計與考量 68
4.3.7 模擬與量測結果 70
4.4 60-GHz CMOS毫米波雙閘極混頻器 75
4.4.1 完整電路設計與考量 75
4.4.2 模擬與量測結果 77
4.5 結果與討論 82
4.5.1 20-GHz CMOS低電壓雙閘極混頻器結果與討論 82
4.5.2 60-GHz CMOS毫米波雙閘極混頻器結果與討論 82


第五章 60-GHz CMOS毫米波射頻前端接收機 83
5.1 60-GHz CMOS毫米波接收機架構介紹 83
5.2 60-GHz CMOS毫米波射頻前端接收機電路架構 86
5.2.1 低雜訊放大器架構與設計流程 86
5.2.2 混頻器架構與設計流程 87
5.2.3 射頻前端電路說明 87
5.3 模擬與量測結果 89
5.3.1 60-GHz CMOS毫米波射頻前端接收機電路模擬結果 89
5.3.2 60-GHz CMOS毫米波射頻前端接收機電路量測結果 89
5.4 結果與討論 94

第六章 結論 95

參考文獻 97

附錄A V-band與W-band毫米波射頻參數量測要點 101
A.1 毫米波量測關鍵零組件介紹 101
A.2 毫米波射頻參數量測要點 103
[1]C. Park and T. S. Rappaport, “Short-range wireless communications for next-generation networks: UWB, 60 GHz millimeter-wave WPAN, and ZigBee,” IEEE Wireless Commun., vol. 14, pp. 70–78, Aug. 2007.
[2]R. fisher, “60 GHz WPAN standardization within IEEE 802.15.3c,” in Proc. Signals, Systems and Electronics (ISSSE), pp. 103–105, Jul. 2007.
[3]RF atmospheric absorption / ducting [Online]. Available : http://www.tscm.com/rf_absor.pdf
[4]J. A. Howarth, A. P. Lauterbach, M. L. J. Boers, L. M. Davis, A. Parker, J. Harrison, J. Rathmell, M. Batty, W. Cowley, C. Burnet, L. Hall, D. Abbott, and N. Weste, “60 GHz radios: enabling next-generation wireless applications,” in Proc. TENCON 2005 region 10, pp. 1–6, Nov. 2005.
[5]T. Tao, M. Gordon, K. Yau, M. T. Yang, and S. P. Voinigescu, “60-GHz PA and LNA in 90-nm RF-CMOS,” in IEEE RFIC Symp. Dig., pp. 91–94, Jun. 2006.
[6]G. Fettweis and R. Irmer, “WIGWAM:system concept development for 1 Gbit/s air interface,” Wireless World Research Forum, Jul. 2005.
[7]IBM’s 60-GHz Page [Online]. Available : http://domino.research.ibm.com/comm/research_projects.nsf/pages/mmwave.sixtygig.html
[8]H. Harada, I. Lakkis, and other contributors, “Merged proposal: new PHY layer and enhancement of MAC for mm-wave system proposal,” IEEE 802.15 Working Group for Personal Area Networks, doc.: IEEE 802.15-07-0943-01-003c, Nov. 2007.
[9]S. K. Reynolds, B. A. Floyd, U. R. Pfeiffer, T. Beukema, J. Grzyb, C. Haymes, B. Gaucher, and M. Soyuer, “A silicon 60-GHz receiver and transmitter chipset for broadband communications,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2820–2831, Dec. 2006.
[10]U. R. Pfeiffer, J. Grzyb, D. Liu, B. Gaucher, T. Beukema, B. A. Floyd, and S. K. Reynolds, “A chip-scale packaging technology for 60-GHz wireless chipsets,” IEEE Trans. Microw. Theory and Tech., vol. 54, no. 8, pp. 3387–3397, Aug. 2006.
[11]A. Boudiaf, D. Bachelet, and C. Rumelhard, “A high-efficiency and low-phase-noise 38-GHz pHEMT MMIC tripler,” IEEE Trans. Microw. Theory and Tech., vol. 48, no. 12, pp. 2546–2553, Dec. 2000.
[12]E. Camargo, Design of FET Frequency Multipliers and Harmonic Oscillators. Reading, MA: Artech House, 1998.
[13]B. Razavi, “A mm-wave CMOS heterodyne receiver with on-chip LO and divider,” ISSCC Dig. Tech. Papers, pp. 188–189, Feb., 2007.
[14]B. Razavi, “A millimeter-wave CMOS heterodyne receiver with on-chip LO and divider,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 477–485, Feb. 2008.
[15]P. Smulders, “Exploiting the 60 GHz band for local wireless multimedia access:prospects and future directions,” IEEE Commun. Mag., vol. 40, pp. 140–147, Jan. 2002.
[16]P. Smulders, “60 GHz radio prospects and future directions,” Commun. and Veh. Tech. symp., pp. 1–8, Nov. 2003.
[17]E. Grass and F. Herzel, M. Piz, Y. Sun and R. Kraemer, “Implementation aspects of Gbit/s communication system for 60 GHz band,” in Proc. 14th Wireless World Research Forum (WWRF), Jul. 2005.
[18]P. Smulders, H. Yang, and I. Akkermans, “On the design of low-cost 60-GHz radios for multigigabit-per-second transmission over short distances,” IEEE Commun. Mag., vol. 45, pp. 44–51, Dec. 2007.
[19]A. Bourdoux, J. Nsenga, W. V. Thillo, F. Horlin, and L. V. Perre, “Air interface and physical layer techniques for 60 GHz WPANs,” Commun. and Veh. Tech. symp. pp. 1–6, Nov. 2006.
[20]劉佳協,60-GHz毫米波CMOS射頻前端RFICs及關鍵被動元件之研究設計,國立成功大學電腦與通訊工程研究所碩士論文,民國九十六年。
[21]L. M. Correia and P. O. Françês, “A propagation model for the estimation of the average received power in an outdoor environment in the millimeter waveband,” in Proc. Veh. Tech. Conf., vol. 3, pp. 1785–1788, Jun. 1994.
[22]李亮輝,802.11a WLAN接收機射頻系統規劃與5 GHz CMOS差動LNA/Mixer之設計,國立成功大學電機工程學系碩士論文,民國九十一年。
[23]C. H. Doan, S. Emami, A. M. Niknejad, and R. W. Brodersen, “Millimeter-wave CMOS design,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 144–155, Jan. 2005.
[24]C. M. Lo, C. S. Lin, and H. Wang, “A miniature V-band 3-stage cascode LNA in 0.13 μm CMOS,” ISSCC Dig. Tech. Papers, pp. 322–323, Feb. 2006.
[25]A. Bevilacqua, and A. M. Niknejad, “An ultrawideband CMOS low-noise amplifier for 3.1–10.6-GHz wireless receivers,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2259–2268, Dec. 2004.
[26]D. J. Allstot, X. Li, and S. Shekhar, “Design considerations for CMOS low-noise amplifier,” in IEEE RFIC Symp. Dig., pp. 97–100, Jun. 2004.
[27]B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001.
[28]B. Johnson, “Thermal agitation of electricity in conductors,” Phys. Rev., vol. 32, pp. 97–109, Jul. 1928.
[29]H. Nyquist, “Thermal agitation of electric charge in conductors,” Phys. Rev., vol. 32, pp. 110–113, Jul. 1928.
[30]T. H. Lee, The Design of CMOS Radio-frequency Integrated Circuits, Cambridge University Press, 2004.
[31]R. P. Jindal, “Compact noise models for MOSFETs,” IEEE Trans. Electron Devices, vol. 53, pp. 2051–2061, Sep. 2006.
[32]朱元凱,應用於802.11a WLAN之5 GHz U-NII頻帶降頻器CMOS RFIC,國立成功大學電機工程學系碩士論文,民國九十一年。
[33]B. Razavi, “A 60-GHz CMOS receiver front-end,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 17–22, Jan. 2006.
[34]D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745–759, May 1997.
[35]S. P. Voinigescu, T. O. Dickson, R. Beerkens, I. Khalid, and P. Westergaard, “A comparison of Si CMOS, SiGe BiCMOS, and InP HBT technologies for high-speed and millimeter-wave ICs,” in IEEE Silicon Monolithic Integrated Circuits in RF Systems (SiRF), pp. 111–114, Sep. 2004.
[36]T. Yao, M. Q. Gordon, K. K. W. Tang, K. H. K. Yau M. T. Yang, P. Schvan, and S. P. Voinigescu, “Algorithmic design CMOS and PAs for 60-GHz radio,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1044–1057, May 2007.
[37]羅玠旻,毫米波CMOS電晶體測試元件,CIC測試元件報告T13-94B-05t,民國94年。
[38]A. M. Mangan, S. P. Voinigescu, M. T. Yang, and M. Tazlauanu, “De-embedding transmission line measurements for accurate modeling of IC designs,” IEEE Trans. Electron Dev., vol. 53, no. 2, pp. 235–241, Feb. 2006.
[39]蔡依修,利用襯墊與傳輸線遮蔽法萃取金氧半場效電晶體的本質雜訊與矽損耗基板模型的開發,CIC測試元件報告T13-96C-01t,民國96年。
[40]H. O. Vickes, M. Ferndahl, A. Masud and H. Zirath, “The influence of the gate leakage current and the gate resistance on the noise and gain performances of 90-nm CMOS for micro- and millimeter-wave frequencies,” IEEE MTT-S Int. Microw. Symp. Dig., vol. 2, pp. 971–974, Jun. 2004.
[41]J. A. Jr., K. T. Kornegay, D. Dawn, S. Pinel, J.Laskar, “60-GHz LNA using a hybrid transmission line and conductive path to ground technique insilicon,” in IEEE RFIC Symp. Dig., pp. 685–688, Jun. 2007.
[42]N. Weste and D. Harris, CMOS VLSI Design. Boston, Addison-Wesely, 2005.
[43]C. L. Ko, C. N. Kuo and Y. Z. Juang, “On-chip transmission line modeling and applications to millimeter-wave circuit design in 0.13 μm CMOS technology,” in IEEE Int. Symp. VLSI design Automation and test (VLSI-DAT), pp. 1–4, Apr. 2007.
[44]C. Inui, I. C. H. Lai, and M. Fujishima, “60 GHz CMOS current-reuse cascade amplifier,” in Proc. IEEE Asia Pacific Microw. Conf., pp. 793–796, Dec. 2007.
[45]S. A. Maas, Microwave Mixers, 2nd edition, Boston: Artech House, 1993.
[46]C. S. Lin, P. S. Wu, H. Y. Chang and H. Wang, “A 9–50-GHz Gilbert-cell down-conversion mixer in 0.13-μm CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 293 – 295, May 2006.
[47]B. M. Motlagh, S. E. Gunnarsson, M. Ferndahl, and H. Zirath, “Fully integrated 60-GHz single-ended resistive mixer in 90-nm CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 1, pp. 25–27, Jan. 2006.
[48]S. A. Maas, “A GaAs MESFET mixer with very low intermodulation,” IEEE Trans. Microw. Theory and Tech., vol. MTT-35, no. 4, pp. 425–429, Apr. 1987.
[49]S. Emami, C. H. Doan, A. M. Niknejad, and R. W. Brodersen, “A 60-GHz down-converting CMOS single-gate mixer,” in IEEE RFIC Symp. Dig., pp. 163–166, Jun. 2005.
[50]C. Tsironis, R. Meierer, and R. Stahlmann, “Dual-gate MESFET mixers,” IEEE Trans. Microw. Theory and Tech., vol. MTT-32, no. 3, pp. 248–255, Mar. 1984.
[51]R. A. Pucel, D. Masse, and R. Bera, “Performance of GaAs MESFET mixers at x-band,” IEEE Trans. Microw. Theory Tech., vol. MTT-24, pp. 351–360, June 1976.
[52]K. Kanazawa, M. Kazumura, S. Nambu, G. Kano, and I. Teramoto, “A GaAs double-balanced dual-gate FET mixer IC for UHF receiver front-end applications,” IEEE Trans. Microw. Theory Tech., vol. MTT-33, pp. 1548–1554, Dec. 1985.
[53]R. C. H. Li, Key Issues in RF/RFIC Circuit Design, 2005.
[54]鐘豪文,超寬頻UWB無線射頻收發機之寬頻CMOS RFICs的設計研究,國立成功大學電腦與通訊工程研究所碩士論文,民國九十五年。
[55]B. Razavi, “Architectures and circuits for RF CMOS receivers,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), pp. 393–400, May. 1998.
[56]B. Razavi, “Design considerations for direct-conversion receivers,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, pp. 428–435, Jun. 1997.
[57]B. Razavi, “RF IC design challenges,” in Proc. Design Automation Conf., pp. 408–413, Jun. 1998.
[58]A. A. Abidi, “Direct-conversion radio transceivers for digital communications”, IEEE J. Solid-State Circuits, vol. 30, no.12, Dec. 1995.
[59]許源佳、許孟列,5.2 GHz無線區域網路CMOS 低雜訊放大器之設計,國家晶片系統中心。
[60]黃秋皇,應用於IEEE 802.11b/g無線區域網路之2.4 GHz CMOS射頻接收機,國立成功大學電機工程學系碩士論文,民國九十二年。
[61]A. Zolfaghari and B. Razavi, “A low-power 2.4-GHz transmitter/receiver CMOS IC,” IEEE J. Solid-State Circuits, vol.38, no. 2, pp. 176–183, Feb. 2003
[62]M. Zargari, D. K. Su, C. P. Yue, S. Rabii, D. Weber, B. J. Kaczynski, S. S. Mehta, K. Singh, S. Mendis, and B. A. Wooley, “A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1688–1694, Dec. 2002.
[63]C. Y. Hsu, C. Y. Chen, and H. R. Chuang, “A 60- GHz millimeter-wave bandpass filter using 0.18-μm CMOS technology,” IEEE Electron Device Lett., vol. 29, no. 3, pp. 246–248, Mar. 2008.
[64]Agilent Technologies / Taiwan Homepage [Online]. Available: http://www.home.agilent.com/agilent/home.jspx?cc=TW&lc=cht&NEWCCLC=TWcht&cmpid=4572
[65]S. Pellerano, Y. Palaskas, and K. Soumyanath, “A 64 GHz 6.5 dB NF 15.5 dB gain LNA in 90 nm CMOS,” in Proc. 33th Eur. Solid-State Circuits Conf. (ESSCIRC), pp. 352–355, Sep. 2007.
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