本論文研製60-GHz CMOS毫米波射頻接收機前端電路，使用標準TSMC CMOS 0.13 μm與TSMC CMOS 0.18 μm製程製作，量測皆採用on-wafer方式進行。論文主要分為兩部分，第一部分介紹IEEE 802.15.3c標準制定歷史以及毫米波相關研究背景，並收集目前發展較具完整性的系統進行說明，最後根據參考文獻估算60-GHz WPAN前端系統之鏈路預算。
第二部份為60-GHz CMOS毫米波射頻前端接收機之電路設計與量測結果。首先為低雜訊放大器的部份，以三級共源極放大器串接架構做為核心放大器並成功降低消耗功率。供應電壓VDD為1.2 V，整體的消耗功率為21.6 mW。57 – 64 GHz增益為5 – 7.6 dB，最佳增益值則出現在50 GHz為11.7 dB，最佳雜訊指數則為7.9 dB。混頻器實現了20-GHz CMOS 0.18-μm低電壓雙閘極混頻器以及60-GHz CMOS 0.13-μm毫米波雙閘極混頻器，利用雙閘極混頻器架構提升LO-RF隔離度，並利用一組LC串聯諧振，成功提昇LO-IF隔離度。雖然20-GHz CMOS低電壓雙閘極混頻器之IF緩衝放大器發生振盪，但混頻器核心功能正常，並經由量測結果得知，所設計之LC串聯諧振成功提昇整體隔離度，埠對埠隔離度皆大於20 dB。至於60-GHz CMOS毫米波雙閘極混頻器部分，設計時於中頻輸出端增加穩定電阻，避免振盪情形發生。量測結果顯示：轉換損耗為2.7 dB，單旁波雜訊指數為21.5 dB，總消耗功率為16.8 mW。最後則為60-GHz CMOS 0.13-μm毫米波射頻前端接收機之研製，承襲上述之架構組合而成，並將IF端輸設計為寬頻匹配，如此可符合不同系統規劃應用。量測結果顯示：RF在47 GHz時，其轉換增益最大值為12.7 dB，3-dB頻寬為4 GHz。雖然達13 GHz之頻漂，但仍證明了使用CMOS 0.13 μm製程實現60-GHz CMOS毫米波收發機電路之可行性。

This thesis presents the design on CMOS RFICs for 60-GHz millimeter-wave wireless receiver RF front-end. The RFICs are fabricated with TSMC CMOS 0.13 μm 1P8M and TSMC CMOS 0.18 μm 1P6M standard processes. In the first part of the thesis, we introduce the millimeter-wave for short-range high data-rate WPAN applications and a brief chronology of the 60-GHz standardization activity. The block diagrams and link budget of the 60-GHz WPAN system are also discussed.
The second part of this thesis presents the design and measurement of CMOS RFICs for 60-GHz millimeter-wave RF front-end. First of all, a three-stage cascaded common source LNA is presented. The LNA has demonstrated a gain of 11.7 dB and a minimum noise figure of 7.9 dB at 50 GHz. The total power consumption is 21.6 mW from a 1.2 V power supply. Compared to the other works using 0.13 μm CMOS, this work has shown that the LNA reduces power consumption successfully. In addition, a 20-GHz CMOS 0.18-μm low voltage dual-gate mixer and a 60-GHz CMOS 0.13-μm millimeter-wave dual-gate mixer are proposed. In order to improve port-to-port isolation, a LC series resonator is designed to bypass the LO signal. On other hand, the 60-GHz CMOS millimeter-wave dual-gate mixer has a conversion loss of 2.7 dB and a SSB NF of 21.5 dB. The total power consumption is 16.8 mW from a 1.2 V power supply. Reasonable agreements of the S-parameters and the conversion loss between simulation and measurement were obtained. Finally, a 60-GHz CMOS 0.13-μm millimeter-wave RF receiver front-end is presented. The measurement shows a maximum conversion gain of 12.7 dB at 47 GHz. The 3-dB bandwidth is 4 GHz. The receiver front-end draws 36.4 mA from a 1.2 V power supply. Although there is 13 GHz frequency offset between simulation and measurement, it is feasible to implement a 60-GHz RF receiver front-end using CMOS 0.13-μm process.

第一章 緒論 1
1.1 短距離無線通訊系統介紹 1
1.2 IEEE 802.15.3c標準制定歷史及毫米波研究背景 3
1.3 論文架構 8

第二章 60-GHz WPAN射頻前端系統簡介 9
2.1 60-GHz WPAN射頻前端系統方塊 9
2.1.1 60-GHz BiCMOS transceiver with 9 GHz IF 10
2.1.2 60-GHz CMOS heterodyne receiver with 20 GHz IF 11
2.1.3 5/60 GHz radio 13
2.1.4 實驗室完整規劃 14
2.2 60-GHz WPAN射頻前端系統鏈路預算 16
2.3 討論 22

第三章 60-GHz CMOS毫米波低雜訊放大器 23
3.1 CMOS毫米波低雜訊放大器介紹 23
3.2 電晶體雜訊來源、量化與雜訊指數 25
3.2.1 電晶體雜訊來源與量化 25
3.2.2 等效輸入雜訊溫度 29
3.3 CMOS毫米波低雜訊放大器設計流程 31
3.3.1 電路架構考量 31
3.3.2 共源極架構雜訊模型 32
3.3.3 電晶體尺寸選擇 33
3.3.4 輸入匹配網路設計 34
3.3.5 介質層等效介電係數驗證 38
3.3.6 完整電路設計流程與考量 41
3.4 V-band量測環境設定與注意事項(詳見附錄A) 43
3.4.1 V-band S-parameter與IP1dB之量測注意事項 43
3.4.2 V-band雙音測試之量測注意事項 44
3.4.3 V-band NF之量測注意事項 45
3.5 模擬與量測結果 46
3.5.1 60-GHz CMOS毫米波低雜訊放大器模擬結果 46
3.5.2 60-GHz CMOS毫米波低雜訊放大器量測結果 46
3.6 結果與討論 50

第四章 20-GHz及60-GHz CMOS雙閘極混頻器 53
4.1 混頻器原理與重要參數介紹 53
4.2 毫米波混頻器架構應用介紹 55
4.2.1 吉伯特混頻器(Gilbert mixer) 56
4.2.2 電阻性混頻器(resistive mixer) 57
4.2.3 單閘極混頻器(single-gate MOSFET mixer) 58
4.2.4 雙閘極混頻器(dual-gate MOSFET mixer) 59
4.3 20-GHz CMOS低電壓雙閘極混頻器 60
4.3.1 雙閘極混頻器偏壓點設計 60
4.3.2 電晶體尺寸選擇 62
4.3.3 LO匹配網路設計考量 66
4.3.4 LC串聯諧振設計考量 66
4.3.5 緩衝放大級 68
4.3.6 完整電路設計與考量 68
4.3.7 模擬與量測結果 70
4.4 60-GHz CMOS毫米波雙閘極混頻器 75
4.4.1 完整電路設計與考量 75
4.4.2 模擬與量測結果 77
4.5 結果與討論 82
4.5.1 20-GHz CMOS低電壓雙閘極混頻器結果與討論 82
4.5.2 60-GHz CMOS毫米波雙閘極混頻器結果與討論 82


第五章 60-GHz CMOS毫米波射頻前端接收機 83
5.1 60-GHz CMOS毫米波接收機架構介紹 83
5.2 60-GHz CMOS毫米波射頻前端接收機電路架構 86
5.2.1 低雜訊放大器架構與設計流程 86
5.2.2 混頻器架構與設計流程 87
5.2.3 射頻前端電路說明 87
5.3 模擬與量測結果 89
5.3.1 60-GHz CMOS毫米波射頻前端接收機電路模擬結果 89
5.3.2 60-GHz CMOS毫米波射頻前端接收機電路量測結果 89
5.4 結果與討論 94

第六章 結論 95

參考文獻 97

附錄A V-band與W-band毫米波射頻參數量測要點 101
A.1 毫米波量測關鍵零組件介紹 101
A.2 毫米波射頻參數量測要點 103

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