1.Aurongzeb, D., S. Patibandla, and M. Holtz, APL, 86 (2005) 103107, “Self-assembly of faceted Ni nanodots on Si(111)”.
2.Berbezier, I, A. Karmous, A. Ronda, A. Sgarlata, A. Balzarotti, P. Castrucci, M. Scarselli, and M. De Crescenzi, APL, 89 (2006) 063122, “Growth of ultrahigh-density quantum-confined germanium dots on SiO2 thin films”.
3.Cabrera, A.L., M. Pino-Leiva, V. Fuenzalida, and R.A. Za´rate, Journal of Physics and Chemistry of Solids, 60 (1999) 791, “Characterization of magnetic iron and nickel vapor deposited films”.
4.Cammarata, R.C., C.V. Thompson, C. Hayzelden, and K. N. Tu, Journal of Materials Research, 5 (1990) 2133, “Silicide precipitation and silicon crystallization in nickel implanted amorphous silicon thin films”.
5.Canut, B., M.G. Blanchin, V. Teodorescu, and A. Traverse, Journal of Non-Crystalline Solids, 353 (2007) 2646, “Structure of Ni/SiO2 films prepared by sol–gel dip coating”.
6.Chen, Jian-Hao, Tan-Fu Lei, Dolf Landheer, Xiaohua Wu, Jian Liu, and Tien-Sheng Chaod, Electrochemical and Solid-State Letters, 10 (2007) H302, “Si Nanocrystal Memory Devices Self-Assembled by In Situ Rapid Thermal Annealing of Ultrathin a-Si on SiO2”.
7.Chi, D.Z., R.T.P. Lee, and A.S.W. Wong, Thin Solid Films, 515 (2007) 8102, “Addressing materials and integration issues for NiSi silicide contact metallization in nano- scale CMOS devices”.
8.Depas, M., B. Vermeire, P. W. Mertens, R. L. Van Meirhaeghe, and M. M. Heyns, Solid-State Electronics, 38 (1995) 1465, “Determination of tunnelling parameters in ultra-thin oxide layer poly-Si/SiO2/Si structures”.
9.Ding, Sei-Jin, Min Zhang, Wei Chen, David Wei Zhang, and Li-Kang Wang, Journal of Electronic Materials, 36(2007) 253, “Memory Effect of Metal-Insulator-Silicon Capacitor with HfO2-Al2O3 Multilayer and Hafnium Nitride Gate”.
10.Dufourcq, J., P. Mur, M.J. Gordon, S. Minoret, R. Coppard, and T. Baron, Materials Science and Engineering C, xx (2006) xxx, “Metallic nano-crystals for f lash memories”.
11.Eiji, Takeda, Norio Suzuki, and Takaaki Hagiwara, IEDM, 00 (1983) 396, “Device performance degradation due to hot-carrier injection at energies below the Si-Si02 energy barrier”.
12.FuHsiang, K., Hsin-Chiang You, and Tan-Fu Lei, APL, 89 (2006) 252111, “Sol-gel-derived double-layered nanocrystal memory”.
13.Ghoshtagore, R. N., Journal of Applied Physics, 40 (1969) 4374, “Diffusion of nickel in amorphous silicon dioxide and silicon nitride films”.
14.Gritsenko, V.A., K.A. Nasyrov, D.V. Gritsenko, Yu.N. Novikov, J.H. Lee, J.-W. Lee, C.W. Kim, and Hei Wong, Microelectronic Engineering, 81 (2005) 530, “Modeling of a EEPROM device based on silicon quantum dots embedded in high-k dielectrics”.
15.Herbert, B. Michaelson, Journal of Applied Physics, 48 (1977) 4729, “The work function of the elements and its periodicty”.
16.Ielmini, D., A. S. Spinelli, and A. L. Lacaita, Microelectronic Engineering, 80 (2005) 321, “Recent developments on Flash memory reliability”.
17.Jung, Yup Yang, Kap Soo Yoon, Won Joon Choi, Young Ho Do, Ju Hyung Kim, Chae Ok Kim, and Jin Pyo Hong, Applied Physics, 7 (2007) 147, “Cobalt metal nanoparticles embedded in SiO2 dielectric layer for the application of nonvolatile memory”.
18.Kouvatsos, D.N., V. Ioannou-Sougleridis, and A. G. Nassiopoulou, APL, 82 (2003) 397, “Charging effects in silicon nanocrystals within SiO2 layers, fabricated by chemical vapor deposition, oxidation, and annealing”.
19.Laegu, Kang, Katsunori Onishi, Yongjoo Jeon, Byoung Hun Lee, Changseok Kang, Wen-Jie Qi, Renee Nieh, Sundar Gopalan, Rino Choi, and Jack C. Lee, IEDM, 00 (2000) 35, “MOSFET devices with polysilicon on single-layer HfO2 high-κ dielectrics”.
20.Lee, Chungho, Jami Meteer, Venkat Narayanan, and Edwin C. Kan, Journal of Electronic Materials, 34 (2005) 1, “Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications”.
21.Lee, Jong Jin, and Dim-Lee Kwong, Electron Devices, 52 (2005) 507, “Metal nanocrystal memory with high-κ tunneling barrier for improved data retention”.
22.Lenzlinger, M., and E. H. Snow, Journal of Applied Physics, 40 (1969) 278, “Fowler-nordheim tunneling into thermally grown SiO2”.
23.Lin, Yu-Hsien, Chao-Hsin Chien, Ching-Tzung Lin, Chun-Yen Chang, and Tan-Fu Lei, IEEE Electron Device Letters, 26 (2005) 154, “High-performance nonvolatile HfO2 nanocrystal memory”.
24.Lin, Gong-Ru, Hao-Chung Kuo, Huang-Shen Lin, and Chih-Chiang Kao, APL, 89 (2006) 073108, “Rapid self-assembly of Ni nanodots on Si substrate covered by a less-adhesive and heat-accumulated SiO2 layers”.
25.Liu, Zengtao, Chungho Lee, Venkat Narayanan, Gen Pei, and Edwin Chihchuan Kan, Electron Devices, 49 (2002) 1606, “Metal nanocrystal memories—part I: device design and fabrication”.
26.Liu, Zengtao, Chungho Lee, Venkat Narayanan, Gen Pei, and Edwin Chihchuan Kan, Electron Devices, 49 (2002) 1614, “Metal nanocrystal memories—part II: electrical characteristics”.
27.Lu, W., and Z. Suo, Physical Review B, 65 (2002) 085401, “Symmetry breaking in self-assembled monolayers on solid surfaces: Anisotropic surface stress”.
28.Ma, L.P., J. Liu, and Y. Yang, APL, 80 (2002) 2997, “Organic electrical bistable devices and rewritable memory cells”.
29.Manabu, Itsumi, and Susumu Muramoto, Proc. Symp. VLSI Technol, (1985) 22, “Gate oxide thinning limit influenced by gate materials”.
30.Mayr, S.G., and K. Samwer, Physical Review Letters, 87 (2001) 036105-1, “Model for intrinsic stress formation in amorphous thin films”.
31.Normand, P., E. Kapetanakis, P. Dimitrakis, D. Tsoukalas, K. Beltsios, Cherkashin, C. Bonafos, G. Benassayag, H. Coffin, A. Claverie, V. Soncini, A. Agarwal, and M. Ameen, APL, 83 (2003) 168, “Effect of annealing environment on the memory properties of thin oxides with embedded Si nanocrystals obtained by low-energy ion-beam synthesis”.
32.Oswald, S., and W. Bruckner, Surf. Interface Anal., 36 (2004) 17, “XPS depth profile analysis of non-stoichiometric NiO films”.
33.Perego, M., S. Ferrari, M. Fanciulli, G. Ben Assayag, C. Bonafos, M. Carrada, and A. Claverie, Journal of Applied Physics, 95 (2004) 257, “Detection and characterization of silicon nanocrystals embedded in thinoxide layers”.
34.Roberto, Bez, Emilio Camerlenghi, Alberto Modelli, and Angelo Visconti, Proceedings of the IEEE, 91 (2003) 489, “Introduction to Flash memory”.
35.Stefan, Lai, and Tyler Lowrey, IEDM, 01 (2001) 803, “OUM-A180 nm nonvolatile memory cell element technology for stand alone and embedded applications”.
36.Samanta, S.K., Won Jong Yoo, Ganesh Samudra, Eng Soon Tok, L. K. Bera, and N. Balasubramanian, APL, 87 (2005) 113110, “Tungsten nanocrystals embedded in high-k materialsfor memory application”.
37.Takata, M., S. Kondoh, T. Sakaguchi, H. Choi, J-C. Shim, H. Kurino, and M. Koyanagi, IEDM, 03 (2003) 553, “New non-volatile memory with extremely high density metal nano-dots”.
38.Takeshi, Sakaguchi, Youn-Gi Hong, Motoki Kobayashi, Masaaki Takata, Hoon Choi, Jeoung-Chill Shim, Hiroyuki Kurino, and Mitsumasa Koyanagi, Japanese Journal of Applied Physics, 43 (2004) 2203, “Proposal of new nonvolatile memory with magnetic nano-dots”.
39.Ueda, Koji, Taizoh Sadoh, Atsushi Kenjo, Fumiya Shoji, Kaoru Sato, Hiroyuki Kurino, Mitsumasa Koyanagi, and Masanobu Miyao, Thin Solid Films, 508 (2006) 178, “Morphological change of Co-nanodot on SiO2 by thermal treatment”.
40.Vitos, L., A.V. Ruban, H.L. Skriver, and J. Kollar, Surface Science, 411 (1998) 186, “The surface energy of metals”.
41.Wen, Luh Yang, Tien Sheng Chao, Chun-Ming Cheng, Tung Ming Pan, and Tan Fu Lei, Electron Devices, 48 (2001) 1304, “High quality interpoly dielectrics deposited on the nitrided-polysilicon for nonvolatile memory devices”.
42.Yang, F.M., T. C. Chang, P. T. Liu, U. S. Chen, P. H. Yeh, Y. C. Yu, J. Y. Lin, S. M. Sze, and J. C. Lou, APL, 90 (2007) 222104, “Nickel nanocrystals with HfO2 blocking oxide for nonvolatile memory application”.
43.Zhenrui, Yu, Mariano Aceves, Jesus Carrillo, and Rosa L�櫝ez-Estopier, Thin Solid Films, 515 (2006) 2366, “Charge trapping and carrier transport mechanism in silicon-rich silicon oxynitride”.
44.Zhu, W.J., Tso-Ping Ma, Takashi Tamagawa, J. Kim, and Y. Di, Electron Devices, 23 (2002) 97, “Current transport in metal/hafnium oxide/silicon structure”.
45.郭正次及朝春光,“奈米結構材料科學”,全華科技股份有限公司,2004年,P. 2-4
46.黃調元,“記憶體元件與製程”,2007年,P. 67
47.魏拯華, “Beyond the baseline memory —次世代記憶體技術分析與評比”, 奈米通訊, 2007.02 P1348.蘇元宏,國立聯合大學電子工程研究所碩士論文,“以漏電流分流模型分析堆疊型氮化氧化層中缺陷陷阱產生位置及其對有效遷移率衰減之影響”,2006,P. 9.