高速數位類比轉換器是目前高效能系統，如資料通訊系統中不可獲缺的主要電路。然而電流驅動式數位類比轉換器因為製程不匹配效能往往受靜態和動態線性度限制。在本篇論文，主要設計一個簡單的隨機架構去改善製程不匹配。我們利用多輸入多輸出多工器架構再配合隨機產生器讓原本固定的線路去隨機改變，再配合特殊的電流源開關的佈局去改善不同製程的改變，我們可以打亂諧波，將能量平均分散到noise floor而增加SFDR。
本論文是配合上述簡單隨機架構的一個12位元250MHz數位類比轉換器，在數位類比轉換器電路的實現，切換電流源式是一個很好的實現方法。在數位類比轉換器中包含在較低的4位元為2進位權重架構和較高的8位元為含有隨機匹配的溫度計編碼架構。除此之外，為了增進數位類比轉換器的動態效能及提高解析度與元件間的匹配，分別使用了抑制突波的拴鎖器和特殊的佈局，來增加數位類比轉換器的效能。同時也考量了在佈局繞線時產生的寄生電容，所造成速度還有信號不同步的效應。數位類比轉換器採用TSMC 0.18 µm 1P6M mixed‐signal CMOS 製程來實現，沒有部分隨機架構整體晶片的面積為1.788 mm2，另外有含部份隨機架構整體晶片面積為1.838 mm2。

Current-Steering digital-to-analog converters (DACs) are very significant blocks of nowadays high-performance systems, such as data communication links using multilevel signaling. However, these current-steering DACs suffer from the element mismatch of technologies and this limits both the static and dynamic performance. This thesis proposes a simple random structure to improve the element mismatch is presented. We can use a multiplexer with 8-bit input and 8-bit output, to implement the random selection. The random generator controls the selection of the element in the MSB part so that the harmonics caused by mismatch can be attenuated. The simple random structure can be used to randomize tones such that spurious-free dynamic range is increased. To cooperate with a special geometrical arrangement of unit cells in the current sources of the MSB, along with a new switching sequence, results in full cancellation of gradient errors.
Utilizing the simple random structure, a 12-bit 250-MSample/s current-steering D/A converter is implemented in this thesis. The DAC includes a 4-bit binary-coded LSBs, 8-bit MSBs with thermometer decoders, and random element matching. The differential switches of current sources are controlled by de-glitch latch. The routing complexity and parasitic capacitance have to be considered for speed and signal synchronization.
12-bit current-steering D/A converters in a TSMC 0.18μm CMOS technology are presented. The simulation results of a 12-bit current-steering D/A converter with the partial random element matching show that with the signal frequency of 100.83 MHz at the update rate of 250 MHz, the SFDR is 66.4 dB. The differential nonlinearity and integral nonlinearity are below 0.5 and 0.7 least significant bits (LSB’s), respectively. The converter consumers a total power of 75 mW and its active area is 1.838 mm2. The simulation results of D/A converter without the partial random element matching shows that with the signal frequency of 100 MHz at the update rate of 500 MHz, the SFDR is 68.9 dB. The differential nonlinearity and integral nonlinearity are below 0.8 and 0.8 LSB’s, respectively. The converter consumers a total power of 73 mW and its active area is 1.788 mm2.

Table of Contents
Abstract (Chinese) I
Abstract (English) II
Acknowledgment IV
Table of Contents V
List of Figures VII
List of Tables XI
Chapter 1. Introduction1
1.1Motivation 1
1.2Organization 2
Chapter 2. Nyquist-Rate Digital-to-Analog Converter 3
2.1 Ideal D/A converter 3
2.2 Performance Metrics 4
2.2.1 Static Performance 4
2.2.2 Dynamic Performance 9
2.2.3 Dynamic range 11
2.3 Binary Weighted DAC Architecture 12
2.3.1 R-2R Ladder DAC 13
2.3.2 Charge Redistribution DAC 14
2.3.3 Current-Mode DAC 15
2.4 Thermometer Coded DAC Architecture 17
2.5 Hybrid DAC Architecture 18
2.6 Summary 19
Chapter 3. System Analysis of DAC Design 20
3.1 Major Error Sources in Current-steering DACs 20
3.2 Finite output impedance of current source 21
3.3 Current Source Mismatch 24
3.4 Switched Gate Driver 31
3.5 Random routing 33
3.6 Summary 36
Chapter 4. Circuit Design of DAC 37
4.1 The System Structure of DAC 37
4.2 Digital Circuits 39
4.2.1 Thermometer decoder 40
4.2.2 Randomizer 41
4.2.3 High speed latch 43
4.3 Current Cell 45
4.3.1 Implementation of Switch Unit Current Cell 45
4.3.2 Reference Current Generation 47
4.4 Layout 48
4.5 Summary 54
Chapter 5. Simulation and Measurement Results 55
5.1 Simulation results 55
5.2 Test Circuits 59
5.3 Measurement Results 61
Chapter 6. Conclusions and Future Work 66
Reference 68

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