臺灣博碩士論文加值系統

在這論文中, 我們設計了一個H.264 CAVLC和CABAC熵解碼器的可合成電路, 我們利用Xilinx Vertex 5-based FPGA發展版, ML506, 和reference software JM 12.2來驗證我們的電路. 我們只利用了7000個slice (發展版的21%) 在50MHz下, 我們CAVLD和CABAD的效能可以達到11mbps和8mbps

In this thesis, we designed a synthesizable RTL model of the entropy decoder (CAVLC and CABAC) for the AVC (a.k.a. H.264) video coding standard. The design has been verified on the Xilinx Vertex 5-based FPGA development board, ML506, using full system verification with the AVC/H.264 reference software JM 12.2. The size of the combined CAVLD and CABAD logic is reasonably small. It only occupies about 7000 slices (21% logic resource of the target device). At a clock rate of 50MHz, the performance of the design can achieve decoding of bitrates over 11 mbps for CAVLD and 8 mbps for CABAC.

Chapter 1. Introduction 1
1.1. Motivation 1
1.2. Target Platform 2
1.3. Outline of the Thesis 4
Chapter 2. Previous Work 5
2.1. CAVLD 5
2.2. CABAD 6
Chapter 3. Design of the CAVLD Logic 9
3.1. Introduction to the CAVLD Entropy Decoder 9
3.1.1. Algorithm of CAVLD 9
3.2. Overall System Architecture 11
3.2.1. AMBA AHB BUS Wrapper for CAVLD 11
3.2.2. CAVLD Top Module 13
3.3. State Controller 15
3.3.1. Interface of State Controller 15
3.3.2. States of the Controller 18
3.3.3. Barrel Shifter 20
3.4. Bitstream Preprocessing Logics 22
3.4.1. First One Detector 22
3.4.1.1. Interface of First One Detector 22
3.4.1.2. Architecture of First One Detector 23
3.4.2. Switch Input Module 24
3.4.2.1. Switch_input_1 Module 24
3.4.2.1.1. Interface of Switch_input_1 Module 24
3.4.2.1.2. Architecture of switch_input_1 Module 25
3.4.2.2. Switch_input_2 Module 26
3.4.2.2.1. Interface of switch_input_2 Module 26
3.4.2.2.2. Architecture of switch_input_2 Module 27
3.5. Coeff_token Decoder 27
3.5.1. Interface of Coeff_token Decoder 27
3.5.2. Architecture of Coeff_token Decoder 29
3.6. Trailing_ones Calculator 31
3.6.1. Interface of Trailing_ones Calculator 31
3.6.2. Architecture of Trailing_ones Calculator 32
3.7. Level Decoder 33
3.7.1. Interface of Level Decoder 33
3.7.2. Architecture of Level Decoder 35
3.8. Total_zeros Decoder 40
3.8.1. Interface of Total_zeros Decoder 40
3.8.2. Architecture of Total_zeros Decoder 41
3.9. Run_before Decoder 43
3.9.1. Interface of Run_before Decoder 43
3.9.2. Architecture of Run_before Decoder 45
3.10. A CAVLD Decoding Example 46
Chapter 4. Design of the CABAD Logic 53
4.1. Introduction to the CABAD Entropy Decoder 53
4.1.1. Algorithm of CABAD 53
4.2. Overall System Architecture 54
4.2.1. AMBA AHB BUS Wrapper for CABAD 54
4.2.2. CABAD Top Module 55
4.3. Binary Arithmetic Coding 58
4.3.1. Normal Decoding Process (AC_Regular_mode) 59
4.3.1.1. Interface of Normal Decoding Process 60
4.3.1.2. Flow Chart of Normal Decoding Process 62
4.3.1.3. Architecture of Normal Decoding Process 62
4.3.2. Bypass Decoding Process (AC_Bypass_mode) 67
4.3.2.1. Interface of Bypass Decoding Process 68
4.3.2.2. Flow Chart of Bypass Decoding Process 68
4.3.2.3. Architecture of Bypass Decoding Process 69
4.3.3. Final Decoding Process (AC_Final_mode) 71
4.3.3.1. Interface of Final Decoding Process 71
4.3.3.2. Flow Chart of Final Decoding Process 72
4.3.3.3. Architecture of Final Decoding Process 73
4.4. Initialization for context variables 76
4.4.1. Interface of Initialization for context variables 76
4.4.2. Architecture of Initialization for context variables 77
4.5. State Controller for each Syntax Element Controller 79
4.6. MB Skip Flag 81
4.6.1. Interface of MB Skip Flag 81
4.6.2. Flow Chart of MB Skip Flag 84
4.7. MB Type 84
4.7.1. Interface of MB Type 84
4.7.2. Flow Chart of MB Type in I_slice 85
4.7.3. Flow Chart of MB Type in P_slice 87
4.7.4. Flow Chart of MB Type in B_slice 88
4.8. Sub MB Type 91
4.8.1. Interface of Sub MB Type 92
4.8.2. Flow Chart of Sub MB Type in P_slice 92
4.8.3. Flow Chart of Sub MB Type in B_slice 93
4.9. Intra Prediction Mode for Luma4x4 95
4.9.1. Interface of Intra Prediction Mode for Luma4x4 95
4.9.2. Flow Chart of Intra Prediction Mode for Luma4x4 96
4.10. Intra Prediction Mode for Chroma 96
4.10.1. Interface of Intra Prediction Mode for Chroma 96
4.10.2. Flow Chart of Intra Prediction Mode for Chroma 97
4.11. Reference Frame Index 98
4.11.1. Interface of Reference Frame Index 98
4.11.2. Flow Chart of Reference Frame Index 99
4.12. Motion Vector Difference 99
4.12.1. Interface of Motion Vector Difference 100
4.12.2. Flow chart of Motion Vector Difference 101
4.13. Coded Block Pattern 101
4.13.1. Interface of Coded Block Pattern 101
4.13.2. Flow Chart of Coded Block Pattern 102
4.14. MB Based Quantization Parameter 103
4.14.1. Interface of MB Based Quantization Parameter 103
4.14.2. Flow Chart of MB Based Quantization Parameter 103
4.15. Coded Block Flag 104
4.15.1. Interface of Coded Block Flag 104
4.15.2. Flow Chart of Coded Block Flag 105
4.16. Significance Map 106
4.16.1. Interface of Significance Map 106
4.16.2. Flow Chart of Significance Map 107
4.17. Level Information 108
4.17.1. Interface of Level Information 108
4.17.2. Flow Chart of Level Information 109
4.18. A CABAD Decoding Example 110
Chapter 5. Experimental Results 115
5.1. Synthesis Results of the Proposed Design 115
5.2. Performance of the Proposed Design 116
5.2.1. Performance of the CAVLD Logic 116
5.2.2. Performance of the CABAD Logic 119
5.2.3. Comparisons with Previous Work 122
5.2.3.1. Comparison of CAVLD Logic with the Design in [8] 122
5.2.3.2. Performance of CABAD Logic 123
5.2.4. Performance Analysis on Target Platform 124
Chapter 6. Conclusions and Future Work 126
References 127

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