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研究生:張守為
研究生(外文):Shou-Wei Chang
論文名稱:一個在異質多核心系統晶片平台的並行程式架構
論文名稱(外文):A Concurrent Programming Framework for Heterogeneous Multi-Core SoC Platforms
指導教授:蔡錫鈞蔡錫鈞引用關係李政崑
指導教授(外文):Shi-Chun TsaiJenq-Kuen Lee
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊科學與工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:英文
論文頁數:40
中文關鍵詞:並行程式程式設計模型軟體架構微核心處理器內部通訊多核心系統晶片作業系統嵌入式系統
外文關鍵詞:concurrent programmingprogramming modelsoftware frameworkmicrokernelinter-processor communicationmulti-coreSoCoperation systemembedded system
相關次數:
  • 被引用被引用:0
  • 點閱點閱:232
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  • 收藏至我的研究室書目清單書目收藏:0
對處理器設計者來說,同時要降低功率消耗以及增進效能是一項關鍵的重要工作。這幾年來,因為具有高效能及低功率消耗的優勢,所以異質多核心系統晶片被大量的採用在嵌入式系統中。為了要讓軟體開發者能更有效的在採用異質多核心系統晶片的系統上開發應用程式,已有多數的研究著手於在這樣的系統上發展程式設計模型(programming model)。程式設計模型的實作可以是程式語言,函式庫,或者是其他型式的軟體架構。在本篇論文中,我們提出了一個具有可移植性,有彈性的以及輕量的並行程式架構。此種架構提供了簡化應用程式開發的服務以及改善執行效能以應付在採用異質多核心系統晶片的系統上的多媒體應用程式的時效性需求。這樣的一個軟體架構由一個微核心及一個雙核通訊模組所組成以便有效地管理系統資源以及處理處理器內部通訊的需求。我們實作此軟體架構於TI OMAP5912 OSK 平台,其為一種異質多核心系統晶片架構。實驗結果顯示我們的微核心比TI DSP/BIOS 核心快。時間量測方法參考由TI 所提供的針對DSP/BIOS 功能的時效標準檢查程式(timing benchmarks) 的應用報告中所描述的方法, 這份應用報告也提供了對於DSP/BIOS APIs 的時效量測數據。由pCore 所提供的工作管理及行程間通訊的平均改善效能分別為53% 與58%。我們也提供了軟體測試套件來驗證我們所提出的微核心的穩定性。
It is a challenge for processor designers to reduce the power consumption and improve the performance simultaneously. In recent years, the heterogeneous multi-core SoC chips have been widely deployed in embedded systems because such architectures have the advantages of high performance and low power consumption. In order to make it more effective for software developers to develop applications on heterogeneous multi-core SoC systems, much research has been conducted to develop programming models on such systems. The implementation of programming models could be programming languages, libraries or other forms of software framework. In this thesis, we propose a concurrent programming framework whose advantages are retargetable, flexible, and lightweight. This framework provides services to facilitate the development of applications and improve performance to meet timing requirements of multimedia applications on heterogeneous multi-core SoC systems. Such the software framework comprises one microkernel and one dual-core communication module to manage system resources efficiently and handle inter-processor communication requests. We implement our software framework on the TI OMAP5912 OSK platform that is a heterogeneous multi-core SoC architecture. The experimental results show that the our microkernel is faster than the TI DSP/BIOS kernel. The methods of time measurement refer to the methods described in the application report, provided by TI, of timing benchmarks for DSP/BIOS functions and this application report also provides timing results for DSP/BIOS APIs. The average performance improvements of task management and inter-process communication provided by pCore are 53% and 58% respectively. We also provide the software testing suite to verify the stability of the proposed microkernel.
Contents vi
List of Figures viii
List of Tables x
1 Introduction 1
2 Background 6
2.1 DSP/BIOS Kernel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 DSPLinux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Multiprocessor Communication Models . . . . . . . . . . . . . . . . . 9
3 Design and Implementation 12
3.1 Software Framework Overview . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Design Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 pCore Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1 Task Management . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.2 Scheduler Implementation . . . . . . . . . . . . . . . . . . . . 20
3.3.3 Semaphore and Mailbox . . . . . . . . . . . . . . . . . . . . . 23
3.3.4 Hardware Abstraction Layer . . . . . . . . . . . . . . . . . . . 23
3.4 pCore Bridge Implementation . . . . . . . . . . . . . . . . . . . . . . 24
vi
4 Experimental Results 28
4.1 Environment Overview and Setting . . . . . . . . . . . . . . . . . . . 28
4.2 Stable Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Conclusion and Future Work 36
5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
[1] G. McNutt and T. Fischer, “Using Linux to Control DSP Algorithms in Mixed-
Processor Systems,” Embedded Edge, pp. 8–13, October 2001.
[2] G. E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics,
vol. 38, no. 8, pp. 114–117, 1965.
[3] N. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir,
and V. Narayanan, “Leakage current: Moore’s law meets static power,”
IEEE Computer, vol. 36, no. 12, pp. 68–75, 2003.
[4] Dana S. Henry, “Hardware mechanisms for efficient interprocessor communication,”
PhD thesis, in Department of Electrical Engineering and Computer
Science, Massachusetts Institute of Technology, 1996.
[5] Cadenux Corp., DSPLinux Board Support Package. [Online]. Available:
http://www.cadenux.com/ridgerun
[6] Texas Instruments Corp., DSP/BIOS Real-Time Kernel and DSP/BIOS Link
Technology.
[7] ——, OMAP Application Processor.
[8] S. Muir and J. Smith, “AsyMOS-an Asymmetric Multiprocessor Operating
System,” In Proceedings of OPENARCH ’98, pp. 25–34, 1998.
[9] Wayne Wolf, “The future of multiprocessor systems-on-chips,” In Proceedings
of the 41st annual conference on Design Automation, pp. 681–685, 2004.
[10] G. Martin, “Overview of the MPSoC design challenge,” In Proceedings of the
43rd annual conference on Design automation, pp. 274–279, 2006.
[11] Chien-Chin Huang, “Microkernel Design and Dual-core Supports for PAC
VLIW DSP Processors,” Master thesis in Department of Computer Science,
National Tsing Hua University, Taiwan, 2007.
[12] David Chih-Wei Chang, I-Tao Liao, Jenq-Kuen Lee, Wen-Feng Chen, Shau-Yin
Tseng, and Chein-Wei Jen, “PAC DSP Core and Application Processors,” In
Proceedings of IEEE International Conference on Multimedia and Expo, pp.
289–292, July 2006.
[13] Texas Instruments Corp., DSP/BIOS Timing Benchmarks for Code Composer
Studio v2.2 Application Report SPRA900B, April 2004.
[14] ——, DSP/BIOS Kernel Technical Overview Application Report SPRA780, August
2001.
[15] A. D. Birrell and B. J. Nelson, “Implementing remote procedure calls,” ACM
Transactions on Computer Systems, vol. 2, no. 1, pp. 39–59, 1984.
[16] Xerox Corp., “Courier: The remote procedure call protocol,” Xerox System
Integration Standard 038112, December 1981.
[17] R. R. Raje, J. I. Williams, and M. Boyles, “Asynchronous Remote Method Invocation
(ARMI) Mechanism for Java,” Concurrency: Practice and Experience,
vol. 9, no. 11, pp. 1207–1211, 1997.
[18] J. Liedtke, “On Micro-kernel Construction,” ACM SIGOPS Operating Systems
Review, vol. 29, no. 5, pp. 237–250, 1995.
[19] ——, “Toward Real Microkernels,” Communications of the ACM, vol. 39, no. 9,
pp. 70–77, 1996.
[20] C. L. Liu and J. W. Layland, “Scheduling Algorithms for Multiprogramming
in a Hard-Real-Time Environment,” Journal of the Association for Computing
Machinery (JACM), vol. 20, no. 1, pp. 46–61, 1973.
[21] A. Silberschatz, P. B. Galvin, G. Gagne, and A. Silberschatz, Operating System
Concepts (6th Edition). Wiley Press, 2001.
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